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Merge branch 'YosysHQ:main' into main

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Akash Levy 2025-11-03 13:38:04 -05:00 • committed by GitHub
commit 76c12f8f8c
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8 changed files with 77 additions and 11 deletions
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frontends/verific/verific.cc
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@ -1636,6 +1636,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
SetIter si ;
Port *port ;
FOREACH_PORT_OF_PORTBUS(portbus, si, port) {
wire->port_id = nl->IndexOf(port) + 1;
import_attributes(wire->attributes, port->GetNet(), nl, portbus->Size());
break;
}