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Bump Yosys to latest

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This commit is contained in:
Akash Levy 2025-09-13 04:35:52 -07:00
commit f5cb0c328f
153 changed files with 1096 additions and 989 deletions
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2
frontends/aiger/aigerparse.cc
View file

@ -909,7 +909,7 @@ void AigerReader::post_process()
module->rename(cell, escaped_s);
}
else
log_error("Symbol type '%s' not recognised.\n", type.c_str());
log_error("Symbol type '%s' not recognised.\n", type);
}
}

4
frontends/aiger2/xaiger.cc
View file

@ -91,7 +91,7 @@ struct Xaiger2Frontend : public Frontend {
std::ifstream map_file;
map_file.open(map_filename);
if (!map_file)
log_error("Failed to open map file '%s'\n", map_filename.c_str());
log_error("Failed to open map file '%s'\n", map_filename);
unsigned int M, I, L, O, A;
std::string header;
@ -388,7 +388,7 @@ struct Xaiger2Frontend : public Frontend {
if (f->eof())
break;
log_assert(!f->fail());
log("input file: %s\n", scratch.c_str());
log("input file: %s\n", scratch);
}
log_debug("co_counter=%d\n", co_counter);

36
frontends/ast/ast.cc
View file

@ -193,7 +193,7 @@ bool AstNode::get_bool_attribute(RTLIL::IdString id)
auto& attr = attributes.at(id);
if (attr->type != AST_CONSTANT)
attr->input_error("Attribute `%s' with non-constant value!\n", id.c_str());
attr->input_error("Attribute `%s' with non-constant value!\n", id);
return attr->integer != 0;
}
@ -1108,9 +1108,9 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
log_assert(ast->type == AST_MODULE || ast->type == AST_INTERFACE);
if (defer)
log("Storing AST representation for module `%s'.\n", ast->str.c_str());
log("Storing AST representation for module `%s'.\n", ast->str);
else if (!quiet) {
log("Generating RTLIL representation for module `%s'.\n", ast->str.c_str());
log("Generating RTLIL representation for module `%s'.\n", ast->str);
}
AstModule *module = new AstModule;
@ -1143,7 +1143,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
{
for (auto& node : ast->children)
if (node->type == AST_PARAMETER && param_has_no_default(node.get()))
node->input_error("Parameter `%s' has no default value and has not been overridden!\n", node->str.c_str());
node->input_error("Parameter `%s' has no default value and has not been overridden!\n", node->str);
bool blackbox_module = flag_lib;
@ -1256,7 +1256,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
for (auto &attr : ast->attributes) {
log_assert((bool)attr.second.get());
if (attr.second->type != AST_CONSTANT)
ast->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
ast->input_error("Attribute `%s' with non-constant value!\n", attr.first);
module->attributes[attr.first] = attr.second->asAttrConst();
}
for (size_t i = 0; i < ast->children.size(); i++) {
@ -1411,7 +1411,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
for (auto& n : design->verilog_packages) {
for (auto &o : n->children) {
auto cloned_node = o->clone();
// log("cloned node %s\n", type2str(cloned_node->type).c_str());
// log("cloned node %s\n", type2str(cloned_node->type));
if (cloned_node->type == AST_ENUM) {
for (auto &e : cloned_node->children) {
log_assert(e->type == AST_ENUM_ITEM);
@ -1432,7 +1432,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
for (const auto& node : child->children)
if (node->type == AST_PARAMETER && param_has_no_default(node.get()))
{
log("Deferring `%s' because it contains parameter(s) without defaults.\n", child->str.c_str());
log("Deferring `%s' because it contains parameter(s) without defaults.\n", child->str);
defer_local = true;
break;
}
@ -1507,7 +1507,7 @@ std::pair<std::string,std::string> AST::split_modport_from_type(std::string name
interface_modport = seglist[1];
}
else { // Erroneous port type
log_error("More than two '.' in signal port type (%s)\n", name_type.c_str());
log_error("More than two '.' in signal port type (%s)\n", name_type);
}
}
return std::pair<std::string,std::string>(interface_type, interface_modport);
@ -1720,7 +1720,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
new_subcell->set_bool_attribute(ID::is_interface);
}
else {
log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname.c_str());
log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname);
}
}
@ -1731,7 +1731,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
} else {
modname = new_modname;
log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
log("Found cached RTLIL representation for module `%s'.\n", modname);
}
return modname;
@ -1750,7 +1750,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
process_module(design, new_ast.get(), false, NULL, quiet);
design->module(modname)->check();
} else if (!quiet) {
log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
log("Found cached RTLIL representation for module `%s'.\n", modname);
}
return modname;
@ -1799,14 +1799,14 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
auto it = parameters.find(child->str);
if (it != parameters.end()) {
if (!quiet)
log("Parameter %s = %s\n", child->str.c_str(), log_signal(it->second));
log("Parameter %s = %s\n", child->str, log_signal(it->second));
named_parameters.emplace_back(child->str, it->second);
continue;
}
it = parameters.find(stringf("$%d", para_counter));
if (it != parameters.end()) {
if (!quiet)
log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(it->second));
log("Parameter %d (%s) = %s\n", para_counter, child->str, log_signal(it->second));
named_parameters.emplace_back(child->str, it->second);
continue;
}
@ -1839,13 +1839,13 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
auto it = parameters.find(child->str);
if (it != parameters.end()) {
if (!quiet)
log("Parameter %s = %s\n", child->str.c_str(), log_signal(it->second));
log("Parameter %s = %s\n", child->str, log_signal(it->second));
goto rewrite_parameter;
}
it = parameters.find(stringf("$%d", para_counter));
if (it != parameters.end()) {
if (!quiet)
log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(it->second));
log("Parameter %d (%s) = %s\n", para_counter, child->str, log_signal(it->second));
goto rewrite_parameter;
}
continue;
@ -1922,11 +1922,9 @@ void AstModule::loadconfig() const
flag_autowire = autowire;
}
void AstNode::input_error(const char *format, ...) const
void AstNode::formatted_input_error(std::string str) const
{
va_list ap;
va_start(ap, format);
logv_file_error(*location.begin.filename, location.begin.line, format, ap);
log_formatted_file_error(*location.begin.filename, location.begin.line, std::move(str));
}
YOSYS_NAMESPACE_END

7
frontends/ast/ast.h
View file

@ -378,7 +378,12 @@ namespace AST
AstNode *get_struct_member() const;
// helper to print errors from simplify/genrtlil code
[[noreturn]] void input_error(const char *format, ...) const YS_ATTRIBUTE(format(printf, 2, 3));
[[noreturn]] void formatted_input_error(std::string str) const;
template <typename... Args>
[[noreturn]] void input_error(FmtString<TypeIdentity<Args>...> fmt, const Args &... args) const
{
formatted_input_error(fmt.format(args...));
}
};
// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code

20
frontends/ast/dpicall.cc
View file

@ -40,7 +40,7 @@ static ffi_fptr resolve_fn (std::string symbol_name)
plugin_name = loaded_plugin_aliases.at(plugin_name);
if (loaded_plugins.count(plugin_name) == 0)
log_error("unable to resolve '%s': can't find plugin `%s'\n", symbol_name.c_str(), plugin_name.c_str());
log_error("unable to resolve '%s': can't find plugin `%s'\n", symbol_name, plugin_name);
void *symbol = dlsym(loaded_plugins.at(plugin_name), real_symbol_name.c_str());
@ -61,7 +61,7 @@ static ffi_fptr resolve_fn (std::string symbol_name)
if (symbol != nullptr)
return (ffi_fptr) symbol;
log_error("unable to resolve '%s'.\n", symbol_name.c_str());
log_error("unable to resolve '%s'.\n", symbol_name);
}
std::unique_ptr<AST::AstNode> AST::dpi_call(AstSrcLocType loc, const std::string &rtype, const std::string &fname, const std::vector<std::string> &argtypes, const std::vector<std::unique_ptr<AST::AstNode>> &args)
@ -74,32 +74,32 @@ std::unique_ptr<AST::AstNode> AST::dpi_call(AstSrcLocType loc, const std::string
ffi_cif cif;
int status;
log("Calling DPI function `%s' and returning `%s':\n", fname.c_str(), rtype.c_str());
log("Calling DPI function `%s' and returning `%s':\n", fname, rtype);
log_assert(GetSize(args) == GetSize(argtypes));
for (int i = 0; i < GetSize(args); i++) {
if (argtypes[i] == "real") {
log(" arg %d (%s): %f\n", i, argtypes[i].c_str(), args[i]->asReal(args[i]->is_signed));
log(" arg %d (%s): %f\n", i, argtypes[i], args[i]->asReal(args[i]->is_signed));
value_store[i].f64 = args[i]->asReal(args[i]->is_signed);
values[i] = &value_store[i].f64;
types[i] = &ffi_type_double;
} else if (argtypes[i] == "shortreal") {
log(" arg %d (%s): %f\n", i, argtypes[i].c_str(), args[i]->asReal(args[i]->is_signed));
log(" arg %d (%s): %f\n", i, argtypes[i], args[i]->asReal(args[i]->is_signed));
value_store[i].f32 = args[i]->asReal(args[i]->is_signed);
values[i] = &value_store[i].f32;
types[i] = &ffi_type_double;
} else if (argtypes[i] == "integer") {
log(" arg %d (%s): %lld\n", i, argtypes[i].c_str(), (long long)args[i]->asInt(args[i]->is_signed));
log(" arg %d (%s): %lld\n", i, argtypes[i], (long long)args[i]->asInt(args[i]->is_signed));
value_store[i].i32 = args[i]->asInt(args[i]->is_signed);
values[i] = &value_store[i].i32;
types[i] = &ffi_type_sint32;
} else if (argtypes[i] == "chandle") {
log(" arg %d (%s): %llx\n", i, argtypes[i].c_str(), (unsigned long long)args[i]->asInt(false));
log(" arg %d (%s): %llx\n", i, argtypes[i], (unsigned long long)args[i]->asInt(false));
value_store[i].ptr = (void *)args[i]->asInt(args[i]->is_signed);
values[i] = &value_store[i].ptr;
types[i] = &ffi_type_pointer;
} else {
log_error("invalid argtype '%s' for argument %d.\n", argtypes[i].c_str(), i);
log_error("invalid argtype '%s' for argument %d.\n", argtypes[i], i);
}
}
@ -116,7 +116,7 @@ std::unique_ptr<AST::AstNode> AST::dpi_call(AstSrcLocType loc, const std::string
types[args.size()] = &ffi_type_pointer;
values[args.size()] = &value_store[args.size()].ptr;
} else {
log_error("invalid rtype '%s'.\n", rtype.c_str());
log_error("invalid rtype '%s'.\n", rtype);
}
if ((status = ffi_prep_cif(&cif, FFI_DEFAULT_ABI, args.size(), types[args.size()], types.data())) != FFI_OK)
@ -155,7 +155,7 @@ YOSYS_NAMESPACE_BEGIN
std::unique_ptr<AST::AstNode> AST::dpi_call(AstSrcLocType, const std::string&, const std::string &fname, const std::vector<std::string>&, const std::vector<std::unique_ptr<AST::AstNode>>&)
{
log_error("Can't call DPI function `%s': this version of yosys is built without plugin support\n", fname.c_str());
log_error("Can't call DPI function `%s': this version of yosys is built without plugin support\n", fname);
}
YOSYS_NAMESPACE_END

70
frontends/ast/genrtlil.cc
View file

@ -56,7 +56,7 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width
if (gen_attributes)
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
that->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
that->input_error("Attribute `%s' with non-constant value!\n", attr.first);
cell->attributes[attr.first] = attr.second->asAttrConst();
}
@ -88,7 +88,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
if (that != nullptr)
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
that->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
that->input_error("Attribute `%s' with non-constant value!\n", attr.first);
cell->attributes[attr.first] = attr.second->asAttrConst();
}
@ -114,7 +114,7 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
that->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
that->input_error("Attribute `%s' with non-constant value!\n", attr.first);
cell->attributes[attr.first] = attr.second->asAttrConst();
}
@ -149,7 +149,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
that->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
that->input_error("Attribute `%s' with non-constant value!\n", attr.first);
cell->attributes[attr.first] = attr.second->asAttrConst();
}
@ -352,7 +352,7 @@ struct AST_INTERNAL::ProcessGenerator
set_src_attr(proc, always.get());
for (auto &attr : always->attributes) {
if (attr.second->type != AST_CONSTANT)
always->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
always->input_error("Attribute `%s' with non-constant value!\n", attr.first);
proc->attributes[attr.first] = attr.second->asAttrConst();
}
current_case = &proc->root_case;
@ -382,7 +382,7 @@ struct AST_INTERNAL::ProcessGenerator
if (found_anyedge_syncs) {
if (found_global_syncs)
always->input_error("Found non-synthesizable event list!\n");
log("Note: Assuming pure combinatorial block at %s in\n", always->loc_string().c_str());
log("Note: Assuming pure combinatorial block at %s in\n", always->loc_string());
log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n");
log("use of @* instead of @(...) for better match of synthesis and simulation.\n");
}
@ -630,7 +630,7 @@ struct AST_INTERNAL::ProcessGenerator
for (auto &attr : ast->attributes) {
if (attr.second->type != AST_CONSTANT)
ast->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
ast->input_error("Attribute `%s' with non-constant value!\n", attr.first);
sw->attributes[attr.first] = attr.second->asAttrConst();
}
@ -1007,7 +1007,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
}
}
if (!id_ast)
input_error("Failed to resolve identifier %s for width detection!\n", str.c_str());
input_error("Failed to resolve identifier %s for width detection!\n", str);
if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM || id_ast->type == AST_ENUM_ITEM) {
if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) {
this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1;
@ -1017,7 +1017,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
if (id_ast->children[0]->type == AST_CONSTANT)
this_width = id_ast->children[0]->bits.size();
else
input_error("Failed to detect width for parameter %s!\n", str.c_str());
input_error("Failed to detect width for parameter %s!\n", str);
}
if (children.size() != 0)
range = children[0].get();
@ -1030,7 +1030,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
// log("---\n");
// id_ast->dumpAst(nullptr, "decl> ");
// dumpAst(nullptr, "ref> ");
input_error("Failed to detect width of signal access `%s'!\n", str.c_str());
input_error("Failed to detect width of signal access `%s'!\n", str);
}
} else {
this_width = id_ast->range_left - id_ast->range_right + 1;
@ -1041,7 +1041,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
this_width = 32;
} else if (id_ast->type == AST_MEMORY) {
if (!id_ast->children[0]->range_valid)
input_error("Failed to detect width of memory access `%s'!\n", str.c_str());
input_error("Failed to detect width of memory access `%s'!\n", str);
this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1;
if (children.size() > 1)
range = children[1].get();
@ -1049,7 +1049,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
auto tmp_range = make_index_range(id_ast);
this_width = tmp_range->range_left - tmp_range->range_right + 1;
} else
input_error("Failed to detect width for identifier %s!\n", str.c_str());
input_error("Failed to detect width for identifier %s!\n", str);
if (range) {
if (range->children.size() == 1)
this_width = 1;
@ -1059,7 +1059,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
while (left_at_zero_ast->simplify(true, 1, -1, false)) { }
while (right_at_zero_ast->simplify(true, 1, -1, false)) { }
if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str);
this_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
} else
this_width = range->range_left - range->range_right + 1;
@ -1193,7 +1193,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
if (!id2ast->is_signed)
sign_hint = false;
if (!id2ast->children[0]->range_valid)
input_error("Failed to detect width of memory access `%s'!\n", str.c_str());
input_error("Failed to detect width of memory access `%s'!\n", str);
this_width = id2ast->children[0]->range_left - id2ast->children[0]->range_right + 1;
width_hint = max(width_hint, this_width);
break;
@ -1266,7 +1266,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
// item expressions.
const AstNode *func = current_scope.at(str);
if (func->type != AST_FUNCTION)
input_error("Function call to %s resolved to something that isn't a function!\n", RTLIL::unescape_id(str).c_str());
input_error("Function call to %s resolved to something that isn't a function!\n", RTLIL::unescape_id(str));
const AstNode *wire = nullptr;
for (const auto& child : func->children)
if (child->str == func->str) {
@ -1302,7 +1302,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
AstNode *current_scope_ast = current_ast_mod == nullptr ? current_ast : current_ast_mod;
for (auto f : log_files)
current_scope_ast->dumpAst(f, "verilog-ast> ");
input_error("Don't know how to detect sign and width for %s node!\n", type2str(type).c_str());
input_error("Don't know how to detect sign and width for %s node!\n", type2str(type));
}
@ -1406,7 +1406,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (flag_pwires)
{
if (GetSize(children) < 1 || children[0]->type != AST_CONSTANT)
input_error("Parameter `%s' with non-constant value!\n", str.c_str());
input_error("Parameter `%s' with non-constant value!\n", str);
RTLIL::Const val = children[0]->bitsAsConst();
RTLIL::IdString id = str;
@ -1420,7 +1420,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
input_error("Attribute `%s' with non-constant value!\n", attr.first);
wire->attributes[attr.first] = attr.second->asAttrConst();
}
}
@ -1429,10 +1429,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// create an RTLIL::Wire for an AST_WIRE node
case AST_WIRE: {
if (!range_valid)
input_error("Signal `%s' with non-constant width!\n", str.c_str());
input_error("Signal `%s' with non-constant width!\n", str);
if (!(range_left + 1 >= range_right))
input_error("Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1);
input_error("Signal `%s' with invalid width range %d!\n", str, range_left - range_right + 1);
RTLIL::IdString id = str;
check_unique_id(current_module, id, this, "signal");
@ -1448,7 +1448,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
input_error("Attribute `%s' with non-constant value!\n", attr.first);
wire->attributes[attr.first] = attr.second->asAttrConst();
}
@ -1464,7 +1464,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
log_assert(children[1]->type == AST_RANGE);
if (!children[0]->range_valid || !children[1]->range_valid)
input_error("Memory `%s' with non-constant width or size!\n", str.c_str());
input_error("Memory `%s' with non-constant width or size!\n", str);
RTLIL::Memory *memory = new RTLIL::Memory;
set_src_attr(memory, this);
@ -1482,7 +1482,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
input_error("Attribute `%s' with non-constant value!\n", attr.first);
memory->attributes[attr.first] = attr.second->asAttrConst();
}
}
@ -1539,11 +1539,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
} else if (flag_autowire)
log_file_warning(*location.begin.filename, location.begin.line, "Identifier `%s' is implicitly declared.\n", str.c_str());
else
input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str);
}
else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM || id2ast->type == AST_ENUM_ITEM) {
if (id2ast->children[0]->type != AST_CONSTANT)
input_error("Parameter %s does not evaluate to constant value!\n", str.c_str());
input_error("Parameter %s does not evaluate to constant value!\n", str);
chunk = RTLIL::Const(id2ast->children[0]->bits);
goto use_const_chunk;
}
@ -1558,11 +1558,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
is_interface = true;
}
else {
input_error("Identifier `%s' doesn't map to any signal!\n", str.c_str());
input_error("Identifier `%s' doesn't map to any signal!\n", str);
}
if (id2ast->type == AST_MEMORY)
input_error("Identifier `%s' does map to an unexpanded memory!\n", str.c_str());
input_error("Identifier `%s' does map to an unexpanded memory!\n", str);
// If identifier is an interface, create a RTLIL::SigSpec with a dummy wire with a attribute called 'is_interface'
// This makes it possible for the hierarchy pass to see what are interface connections and then replace them
@ -1610,7 +1610,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
while (left_at_zero_ast->simplify(true, 1, -1, false)) { }
while (right_at_zero_ast->simplify(true, 1, -1, false)) { }
if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str);
int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
auto fake_ast = std::make_unique<AstNode>(children[0]->location, AST_NONE, clone(), children[0]->children.size() >= 2 ?
children[0]->children[1]->clone() : children[0]->children[0]->clone());
@ -2032,7 +2032,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
set_src_attr(cell, this);
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
input_error("Attribute `%s' with non-constant value!\n", attr.first);
cell->attributes[attr.first] = attr.second->asAttrConst();
}
cell->setParam(ID(FLAVOR), flavor);
@ -2148,7 +2148,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
input_error("Attribute `%s' with non-constant value.\n", attr.first.c_str());
input_error("Attribute `%s' with non-constant value.\n", attr.first);
cell->attributes[attr.first] = attr.second->asAttrConst();
}
if (cell->type == ID($specify2)) {
@ -2203,7 +2203,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
log_file_warning(*location.begin.filename, location.begin.line, "\n");
} else if (str == "$error") {
if (sz > 0)
input_error("%s.\n", children[0]->str.c_str());
input_error("%s.\n", children[0]->str);
else
input_error("\n");
} else if (str == "$fatal") {
@ -2212,11 +2212,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// dollar_finish(sz ? children[0] : 1);
// perhaps create & use log_file_fatal()
if (sz > 0)
input_error("FATAL: %s.\n", children[0]->str.c_str());
input_error("FATAL: %s.\n", children[0]->str);
else
input_error("FATAL.\n");
} else {
input_error("Unknown elaboration system task '%s'.\n", str.c_str());
input_error("Unknown elaboration system task '%s'.\n", str);
}
} break;
@ -2245,7 +2245,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
if (width <= 0)
input_error("Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str());
input_error("Failed to detect width of %s!\n", RTLIL::unescape_id(str));
Cell *cell = current_module->addCell(myid, str.substr(1));
set_src_attr(cell, this);
@ -2272,7 +2272,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
default:
for (auto f : log_files)
current_ast_mod->dumpAst(f, "verilog-ast> ");
input_error("Don't know how to generate RTLIL code for %s node!\n", type2str(type).c_str());
input_error("Don't know how to generate RTLIL code for %s node!\n", type2str(type));
}
return RTLIL::SigSpec();

110
frontends/ast/simplify.cc
View file

@ -180,10 +180,10 @@ void AstNode::annotateTypedEnums(AstNode *template_node)
if (template_node->attributes.count(ID::enum_type)) {
//get reference to enum node:
std::string enum_type = template_node->attributes[ID::enum_type]->str.c_str();
// log("enum_type=%s (count=%lu)\n", enum_type.c_str(), current_scope.count(enum_type));
// log("enum_type=%s (count=%lu)\n", enum_type, current_scope.count(enum_type));
// log("current scope:\n");
// for (auto &it : current_scope)
// log(" %s\n", it.first.c_str());
// log(" %s\n", it.first);
log_assert(current_scope.count(enum_type) == 1);
AstNode *enum_node = current_scope.at(enum_type);
log_assert(enum_node->type == AST_ENUM);
@ -250,7 +250,7 @@ static int range_width(AstNode *node, AstNode *rnode)
{
log_assert(rnode->type==AST_RANGE);
if (!rnode->range_valid) {
node->input_error("Non-constant range in declaration of %s\n", node->str.c_str());
node->input_error("Non-constant range in declaration of %s\n", node->str);
}
// note: range swapping has already been checked for
return rnode->range_left - rnode->range_right + 1;
@ -265,7 +265,7 @@ static int add_dimension(AstNode *node, AstNode *rnode)
[[noreturn]] static void struct_array_packing_error(AstNode *node)
{
node->input_error("Unpacked array in packed struct/union member %s\n", node->str.c_str());
node->input_error("Unpacked array in packed struct/union member %s\n", node->str);
}
static int size_packed_struct(AstNode *snode, int base_offset)
@ -358,7 +358,7 @@ static int size_packed_struct(AstNode *snode, int base_offset)
}
else {
if (packed_width != width)
node->input_error("member %s of a packed union has %d bits, expecting %d\n", node->str.c_str(), width, packed_width);
node->input_error("member %s of a packed union has %d bits, expecting %d\n", node->str, width, packed_width);
}
}
else {
@ -481,7 +481,7 @@ std::unique_ptr<AstNode> AstNode::make_index_range(AstNode *decl_node, bool unpa
dim--; // Step back to the final index / slice
}
else {
input_error("Unsupported range operation for %s\n", str.c_str());
input_error("Unsupported range operation for %s\n", str);
}
std::unique_ptr<AstNode> index_range = std::make_unique<AstNode>(rnode->location, AST_RANGE);
@ -911,7 +911,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
#if 0
log("-------------\n");
log("AST simplify[%d] depth %d at %s:%d on %s %p:\n", stage, recursion_counter, location.begin.filename->c_str(), location.begin.line, type2str(type).c_str(), this);
log("AST simplify[%d] depth %d at %s:%d on %s %p:\n", stage, recursion_counter, location.begin.filename, location.begin.line, type2str(type), this);
log("const_fold=%d, stage=%d, width_hint=%d, sign_hint=%d\n",
int(const_fold), int(stage), int(width_hint), int(sign_hint));
// dumpAst(nullptr, "> ");
@ -963,7 +963,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
if ((memflags & AstNode::MEM2REG_FL_CONST_LHS) && !(memflags & AstNode::MEM2REG_FL_VAR_LHS))
goto verbose_activate;
// log("Note: Not replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str.c_str(), long(memflags));
// log("Note: Not replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str, long(memflags));
continue;
verbose_activate:
@ -978,7 +978,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
}
silent_activate:
// log("Note: Replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str.c_str(), long(memflags));
// log("Note: Replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str, long(memflags));
mem2reg_set.insert(mem);
}
@ -1063,7 +1063,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
Fmt fmt = processFormat(stage, /*sformat_like=*/false, default_base, /*first_arg_at=*/0, /*may_fail=*/true);
if (str.substr(0, 8) == "$display")
fmt.append_literal("\n");
log("%s", fmt.render().c_str());
log("%s", fmt.render());
}
return false;
@ -1135,7 +1135,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
if (current_scope.count(enode->str) == 0)
current_scope[enode->str] = enode.get();
else
input_error("enum item %s already exists in current scope\n", enode->str.c_str());
input_error("enum item %s already exists in current scope\n", enode->str);
}
}
}
@ -1209,7 +1209,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
continue;
wires_are_incompatible:
if (stage > 1)
input_error("Incompatible re-declaration of wire %s.\n", node->str.c_str());
input_error("Incompatible re-declaration of wire %s.\n", node->str);
continue;
}
this_wire_scope[node->str] = node;
@ -1228,7 +1228,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
if (current_scope.count(enode->str) == 0)
current_scope[enode->str] = enode.get();
else
input_error("enum item %s already exists\n", enode->str.c_str());
input_error("enum item %s already exists\n", enode->str);
}
}
}
@ -1268,7 +1268,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
if (current_scope.count(enode->str) == 0)
current_scope[enode->str] = enode.get();
else
input_error("enum item %s already exists in package\n", enode->str.c_str());
input_error("enum item %s already exists in package\n", enode->str);
}
}
}
@ -1499,7 +1499,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
break;
case AST_ENUM:
//log("\nENUM %s: %d child %d\n", str.c_str(), basic_prep, children[0]->basic_prep);
//log("\nENUM %s: %d child %d\n", str, basic_prep, children[0]->basic_prep);
if (!basic_prep) {
for (auto& item_node : children) {
while (!item_node->basic_prep && item_node->simplify(false, stage, -1, false))
@ -1561,10 +1561,10 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
const std::string &type_name = child->children[0]->str;
if (!current_scope.count(type_name))
input_error("Unknown identifier `%s' used as type name\n", type_name.c_str());
input_error("Unknown identifier `%s' used as type name\n", type_name);
AstNode *resolved_type_node = current_scope.at(type_name);
if (resolved_type_node->type != AST_TYPEDEF)
input_error("`%s' does not name a type\n", type_name.c_str());
input_error("`%s' does not name a type\n", type_name);
log_assert(resolved_type_node->children.size() == 1);
auto* template_node = resolved_type_node->children[0].get();
@ -1590,7 +1590,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
}
default:
log_error("Don't know how to translate static cast of type %s\n", type2str(template_node->type).c_str());
log_error("Don't know how to translate static cast of type %s\n", type2str(template_node->type));
}
}
@ -1909,7 +1909,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
}
if (pos == std::string::npos)
input_error("Can't find object for defparam `%s`!\n", RTLIL::unescape_id(paramname).c_str());
input_error("Can't find object for defparam `%s`!\n", RTLIL::unescape_id(paramname));
paramname = "\\" + paramname.substr(pos+1);
@ -1943,11 +1943,11 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
log_assert(children[0]->type == AST_WIRETYPE);
auto type_name = children[0]->str;
if (!current_scope.count(type_name)) {
input_error("Unknown identifier `%s' used as type name\n", type_name.c_str());
input_error("Unknown identifier `%s' used as type name\n", type_name);
}
AstNode *resolved_type_node = current_scope.at(type_name);
if (resolved_type_node->type != AST_TYPEDEF)
input_error("`%s' does not name a type\n", type_name.c_str());
input_error("`%s' does not name a type\n", type_name);
log_assert(resolved_type_node->children.size() == 1);
auto& template_node = resolved_type_node->children[0];
@ -1985,7 +1985,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
// Cannot add packed dimensions if unpacked dimensions are already specified.
if (add_packed_dimensions && newNode->type == AST_MEMORY)
input_error("Cannot extend unpacked type `%s' with packed dimensions\n", type_name.c_str());
input_error("Cannot extend unpacked type `%s' with packed dimensions\n", type_name);
// Add packed dimensions.
if (add_packed_dimensions) {
@ -2030,7 +2030,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
children.insert(children.begin(), std::move(expr));
if (children[1]->type == AST_MEMORY)
input_error("unpacked array type `%s' cannot be used for a parameter\n", children[1]->str.c_str());
input_error("unpacked array type `%s' cannot be used for a parameter\n", children[1]->str);
fixup_hierarchy_flags();
did_something = true;
}
@ -2297,7 +2297,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
AstNode *current_scope_ast = (current_ast_mod == nullptr) ? current_ast : current_ast_mod;
str = try_pop_module_prefix();
for (auto& node : current_scope_ast->children) {
//log("looking at mod scope child %s\n", type2str(node->type).c_str());
//log("looking at mod scope child %s\n", type2str(node->type));
switch (node->type) {
case AST_PARAMETER:
case AST_LOCALPARAM:
@ -2308,9 +2308,9 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
case AST_FUNCTION:
case AST_TASK:
case AST_DPI_FUNCTION:
//log("found child %s, %s\n", type2str(node->type).c_str(), node->str.c_str());
//log("found child %s, %s\n", type2str(node->type), node->str);
if (str == node->str) {
//log("add %s, type %s to scope\n", str.c_str(), type2str(node->type).c_str());
//log("add %s, type %s to scope\n", str, type2str(node->type));
current_scope[node->str] = node.get();
}
break;
@ -2319,7 +2319,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
for (auto& enum_node : node->children) {
log_assert(enum_node->type==AST_ENUM_ITEM);
if (str == enum_node->str) {
//log("\nadding enum item %s to scope\n", str.c_str());
//log("\nadding enum item %s to scope\n", str);
current_scope[str] = enum_node.get();
}
}
@ -2331,7 +2331,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
}
if (current_scope.count(str) == 0) {
if (current_ast_mod == nullptr) {
input_error("Identifier `%s' is implicitly declared outside of a module.\n", str.c_str());
input_error("Identifier `%s' is implicitly declared outside of a module.\n", str);
} else if (flag_autowire || str == "\\$global_clock") {
auto auto_wire = std::make_unique<AstNode>(location, AST_AUTOWIRE);
auto_wire->str = str;
@ -2339,7 +2339,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
current_ast_mod->children.push_back(std::move(auto_wire));
did_something = true;
} else {
input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str);
}
}
if (id2ast != current_scope[str]) {
@ -2562,7 +2562,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
}
if (buf->type != AST_CONSTANT)
input_error("Right hand side of 3rd expression of %s for-loop is not constant (%s)!\n", loop_type_str, type2str(buf->type).c_str());
input_error("Right hand side of 3rd expression of %s for-loop is not constant (%s)!\n", loop_type_str, type2str(buf->type));
varbuf->children[0] = std::move(buf);
}
@ -2778,7 +2778,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
if (type == AST_PRIMITIVE)
{
if (children.size() < 2)
input_error("Insufficient number of arguments for primitive `%s'!\n", str.c_str());
input_error("Insufficient number of arguments for primitive `%s'!\n", str);
std::vector<std::unique_ptr<AstNode>> children_list;
for (auto& child : children) {
@ -2792,7 +2792,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
if (str == "bufif0" || str == "bufif1" || str == "notif0" || str == "notif1")
{
if (children_list.size() != 3)
input_error("Invalid number of arguments for primitive `%s'!\n", str.c_str());
input_error("Invalid number of arguments for primitive `%s'!\n", str);
std::vector<RTLIL::State> z_const(1, RTLIL::State::Sz);
@ -2894,7 +2894,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
auto& range = children[0]->children[0];
if (!try_determine_range_width(range.get(), result_width))
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str);
if (range->children.size() >= 2)
shift_expr = range->children[1]->clone();
@ -3285,7 +3285,7 @@ skip_dynamic_range_lvalue_expansion:;
int width;
if (!try_determine_range_width(the_range.get(), width))
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str);
if (the_range->children.size() >= 2)
offset_ast = the_range->children[1]->clone();
@ -3405,7 +3405,7 @@ skip_dynamic_range_lvalue_expansion:;
auto buf = children[1]->clone();
while (buf->simplify(true, stage, -1, false)) { }
if (buf->type != AST_CONSTANT)
input_error("Failed to evaluate system function `%s' with non-constant value.\n", str.c_str());
input_error("Failed to evaluate system function `%s' with non-constant value.\n", str);
num_steps = buf->asInt(true);
}
@ -3516,7 +3516,7 @@ skip_dynamic_range_lvalue_expansion:;
auto buf = children[0]->clone();
while (buf->simplify(true, stage, width_hint, sign_hint)) { }
if (buf->type != AST_CONSTANT)
input_error("Failed to evaluate system function `%s' with non-constant value.\n", str.c_str());
input_error("Failed to evaluate system function `%s' with non-constant value.\n", str);
RTLIL::Const arg_value = buf->bitsAsConst();
if (arg_value.as_bool())
@ -3563,7 +3563,7 @@ skip_dynamic_range_lvalue_expansion:;
if (id_ast == nullptr && current_scope.count(buf->str))
id_ast = current_scope.at(buf->str);
if (!id_ast)
input_error("Failed to resolve identifier %s for width detection!\n", buf->str.c_str());
input_error("Failed to resolve identifier %s for width detection!\n", buf->str);
if (id_ast->type == AST_WIRE || id_ast->type == AST_MEMORY) {
// Check for item in packed struct / union
@ -3578,7 +3578,7 @@ skip_dynamic_range_lvalue_expansion:;
// TODO: IEEE Std 1800-2017 20.7: "If the first argument to an array query function would cause $dimensions to return 0
// or if the second argument is out of range, then 'x shall be returned."
if (dim < 1 || dim > dims)
input_error("Dimension %d out of range in `%s', as it only has %d dimensions!\n", dim, id_ast->str.c_str(), dims);
input_error("Dimension %d out of range in `%s', as it only has %d dimensions!\n", dim, id_ast->str, dims);
expr_dimensions = dims - dim + 1;
expr_unpacked_dimensions = std::max(id_ast->unpacked_dimensions - dim + 1, 0);
@ -3712,9 +3712,9 @@ skip_dynamic_range_lvalue_expansion:;
auto& node = children[i];
while (node->simplify(true, stage, -1, false)) { }
if (node->type != AST_CONSTANT)
input_error("Failed to evaluate system function `%s' with non-constant control bit argument.\n", str.c_str());
input_error("Failed to evaluate system function `%s' with non-constant control bit argument.\n", str);
if (node->bits.size() != 1)
input_error("Failed to evaluate system function `%s' with control bit width != 1.\n", str.c_str());
input_error("Failed to evaluate system function `%s' with control bit width != 1.\n", str);
control_bits.push_back(node->bits[0]);
}
@ -3817,7 +3817,7 @@ skip_dynamic_range_lvalue_expansion:;
if (current_scope.count(str) == 0)
str = try_pop_module_prefix();
if (current_scope.count(str) == 0 || current_scope[str]->type != AST_FUNCTION)
input_error("Can't resolve function name `%s'.\n", str.c_str());
input_error("Can't resolve function name `%s'.\n", str);
}
if (type == AST_TCALL)
@ -3825,9 +3825,9 @@ skip_dynamic_range_lvalue_expansion:;
if (str == "$finish" || str == "$stop")
{
if (!current_always || current_always->type != AST_INITIAL)
input_error("System task `%s' outside initial block is unsupported.\n", str.c_str());
input_error("System task `%s' outside initial block is unsupported.\n", str);
input_error("System task `%s' executed.\n", str.c_str());
input_error("System task `%s' executed.\n", str);
}
if (str == "\\$readmemh" || str == "\\$readmemb")
@ -3839,12 +3839,12 @@ skip_dynamic_range_lvalue_expansion:;
auto node_filename = children[0]->clone();
while (node_filename->simplify(true, stage, width_hint, sign_hint)) { }
if (node_filename->type != AST_CONSTANT)
input_error("Failed to evaluate system function `%s' with non-constant 1st argument.\n", str.c_str());
input_error("Failed to evaluate system function `%s' with non-constant 1st argument.\n", str);
auto node_memory = children[1]->clone();
while (node_memory->simplify(true, stage, width_hint, sign_hint)) { }
if (node_memory->type != AST_IDENTIFIER || node_memory->id2ast == nullptr || node_memory->id2ast->type != AST_MEMORY)
input_error("Failed to evaluate system function `%s' with non-memory 2nd argument.\n", str.c_str());
input_error("Failed to evaluate system function `%s' with non-memory 2nd argument.\n", str);
int start_addr = -1, finish_addr = -1;
@ -3852,7 +3852,7 @@ skip_dynamic_range_lvalue_expansion:;
auto node_addr = children[2]->clone();
while (node_addr->simplify(true, stage, width_hint, sign_hint)) { }
if (node_addr->type != AST_CONSTANT)
input_error("Failed to evaluate system function `%s' with non-constant 3rd argument.\n", str.c_str());
input_error("Failed to evaluate system function `%s' with non-constant 3rd argument.\n", str);
start_addr = int(node_addr->asInt(false));
}
@ -3860,7 +3860,7 @@ skip_dynamic_range_lvalue_expansion:;
auto node_addr = children[3]->clone();
while (node_addr->simplify(true, stage, width_hint, sign_hint)) { }
if (node_addr->type != AST_CONSTANT)
input_error("Failed to evaluate system function `%s' with non-constant 4th argument.\n", str.c_str());
input_error("Failed to evaluate system function `%s' with non-constant 4th argument.\n", str);
finish_addr = int(node_addr->asInt(false));
}
@ -3888,7 +3888,7 @@ skip_dynamic_range_lvalue_expansion:;
if (current_scope.count(str) == 0)
str = try_pop_module_prefix();
if (current_scope.count(str) == 0 || current_scope[str]->type != AST_TASK)
input_error("Can't resolve task name `%s'.\n", str.c_str());
input_error("Can't resolve task name `%s'.\n", str);
}
@ -3928,7 +3928,7 @@ skip_dynamic_range_lvalue_expansion:;
if (in_param)
input_error("Non-constant function call in constant expression.\n");
if (require_const_eval)
input_error("Function %s can only be called with constant arguments.\n", str.c_str());
input_error("Function %s can only be called with constant arguments.\n", str);
}
size_t arg_count = 0;
@ -4050,7 +4050,7 @@ skip_dynamic_range_lvalue_expansion:;
goto tcall_incompatible_wires;
} else {
tcall_incompatible_wires:
input_error("Incompatible re-declaration of wire %s.\n", child->str.c_str());
input_error("Incompatible re-declaration of wire %s.\n", child->str);
}
}
}
@ -4476,7 +4476,7 @@ std::unique_ptr<AstNode> AstNode::readmem(bool is_readmemh, std::string mem_file
yosys_input_files.insert(mem_filename);
}
if (f.fail() || GetSize(mem_filename) == 0)
input_error("Can not open file `%s` for %s.\n", mem_filename.c_str(), str.c_str());
input_error("Can not open file `%s` for %s.\n", mem_filename, str);
log_assert(GetSize(memory->children) == 2 && memory->children[1]->type == AST_RANGE && memory->children[1]->range_valid);
int range_left = memory->children[1]->range_left, range_right = memory->children[1]->range_right;
@ -4522,7 +4522,7 @@ std::unique_ptr<AstNode> AstNode::readmem(bool is_readmemh, std::string mem_file
char *endptr;
cursor = strtol(nptr, &endptr, 16);
if (!*nptr || *endptr)
input_error("Can not parse address `%s` for %s.\n", nptr, str.c_str());
input_error("Can not parse address `%s` for %s.\n", nptr, str);
continue;
}
@ -5404,7 +5404,7 @@ std::unique_ptr<AstNode> AstNode::eval_const_function(AstNode *fcall, bool must_
#if 0
log("-----------------------------------\n");
for (auto &it : variables)
log("%20s %40s\n", it.first.c_str(), log_signal(it.second.val));
log("%20s %40s\n", it.first, log_signal(it.second.val));
stmt->dumpAst(nullptr, "stmt> ");
#endif
if (stmt->type == AST_WIRE)
@ -5421,7 +5421,7 @@ std::unique_ptr<AstNode> AstNode::eval_const_function(AstNode *fcall, bool must_
// if this variable has already been declared as an input, check the
// sizes match if it already had an explicit size
if (variable.arg && variable.explicitly_sized && variable.val.size() != width) {
input_error("Incompatible re-declaration of constant function wire %s.\n", stmt->str.c_str());
input_error("Incompatible re-declaration of constant function wire %s.\n", stmt->str);
}
variable.val = RTLIL::Const(RTLIL::State::Sx, width);
variable.offset = stmt->range_swapped ? stmt->range_left : stmt->range_right;
@ -5503,7 +5503,7 @@ std::unique_ptr<AstNode> AstNode::eval_const_function(AstNode *fcall, bool must_
if (!range->range_valid) {
if (!must_succeed)
goto finished;
range->input_error("Non-constant range\n%s: ... called from here.\n", fcall->loc_string().c_str());
range->input_error("Non-constant range\n%s: ... called from here.\n", fcall->loc_string());
}
int offset = min(range->range_left, range->range_right);
int width = std::abs(range->range_left - range->range_right) + 1;

2
frontends/blif/blifparse.cc
View file

@ -618,7 +618,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
error:
log_error("Syntax error in line %d!\n", line_count);
error_with_reason:
log_error("Syntax error in line %d: %s\n", line_count, err_reason.c_str());
log_error("Syntax error in line %d: %s\n", line_count, err_reason);
}
struct BlifFrontend : public Frontend {

4
frontends/json/jsonparse.cc
View file

@ -289,7 +289,7 @@ void json_parse_attr_param(dict<IdString, Const> &results, JsonNode *node)
void json_import(Design *design, string &modname, JsonNode *node)
{
log("Importing module %s from JSON tree.\n", modname.c_str());
log("Importing module %s from JSON tree.\n", modname);
Module *module = new RTLIL::Module;
module->name = RTLIL::escape_id(modname.c_str());
@ -367,7 +367,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
port_wire->port_input = true;
port_wire->port_output = true;
} else
log_error("JSON port node '%s' has invalid '%s' direction attribute.\n", log_id(port_name), port_direction_node->data_string.c_str());
log_error("JSON port node '%s' has invalid '%s' direction attribute.\n", log_id(port_name), port_direction_node->data_string);
port_wire->port_id = port_id;

12
frontends/liberty/liberty.cc
View file

@ -47,7 +47,7 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
std::string id = RTLIL::escape_id(std::string(expr, id_len));
if (!module->wires_.count(id))
log_error("Can't resolve wire name %s.\n", RTLIL::unescape_id(id).c_str());
log_error("Can't resolve wire name %s.\n", RTLIL::unescape_id(id));
expr += id_len;
return module->wires_.at(id);
@ -550,7 +550,7 @@ struct LibertyFrontend : public Frontend {
if (cell->id != "cell" || cell->args.size() != 1)
continue;
// log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name).c_str());
// log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name));
std::map<std::string, std::tuple<int, int, bool>> type_map = global_type_map;
parse_type_map(type_map, cell);
@ -582,9 +582,9 @@ struct LibertyFrontend : public Frontend {
{
if (!flag_ignore_miss_dir)
{
log_error("Missing or invalid direction for pin %s on cell %s.\n", node->args.at(0).c_str(), log_id(module->name));
log_error("Missing or invalid direction for pin %s on cell %s.\n", node->args.at(0), log_id(module->name));
} else {
log("Ignoring cell %s with missing or invalid direction for pin %s.\n", log_id(module->name), node->args.at(0).c_str());
log("Ignoring cell %s with missing or invalid direction for pin %s.\n", log_id(module->name), node->args.at(0));
delete module;
goto skip_cell;
}
@ -596,7 +596,7 @@ struct LibertyFrontend : public Frontend {
if (node->id == "bus" && node->args.size() == 1)
{
if (flag_ignore_buses) {
log("Ignoring cell %s with a bus interface %s.\n", log_id(module->name), node->args.at(0).c_str());
log("Ignoring cell %s with a bus interface %s.\n", log_id(module->name), node->args.at(0));
delete module;
goto skip_cell;
}
@ -613,7 +613,7 @@ struct LibertyFrontend : public Frontend {
}
if (!dir || (dir->value != "input" && dir->value != "output" && dir->value != "inout" && dir->value != "internal"))
log_error("Missing or invalid direction for bus %s on cell %s.\n", node->args.at(0).c_str(), log_id(module->name));
log_error("Missing or invalid direction for bus %s on cell %s.\n", node->args.at(0), log_id(module->name));
simple_comb_cell = false;

20
frontends/rpc/rpc_frontend.cc
View file

@ -167,7 +167,7 @@ struct RpcModule : RTLIL::Module {
std::string parameter_info;
for (auto &param : parameters) {
log("Parameter %s = %s\n", param.first.c_str(), log_signal(RTLIL::SigSpec(param.second)));
log("Parameter %s = %s\n", param.first, log_signal(RTLIL::SigSpec(param.second)));
parameter_info += stringf("%s=%s", param.first, log_signal(RTLIL::SigSpec(param.second)));
}
@ -180,7 +180,7 @@ struct RpcModule : RTLIL::Module {
derived_name = "$paramod" + stripped_name + parameter_info;
if (design->has(derived_name)) {
log("Found cached RTLIL representation for module `%s'.\n", derived_name.c_str());
log("Found cached RTLIL representation for module `%s'.\n", derived_name);
} else {
std::string command, input;
std::tie(command, input) = server->derive_module(stripped_name.substr(1), parameters);
@ -437,7 +437,7 @@ struct RpcFrontend : public Pass {
command_path_len_w = SearchPathW(/*lpPath=*/NULL, /*lpFileName=*/command_w.c_str(), /*lpExtension=*/L".exe", /*nBufferLength=*/0, /*lpBuffer=*/NULL, /*lpFilePart=*/NULL);
if (command_path_len_w == 0) {
log_error("SearchPathW failed: %s\n", get_last_error_str().c_str());
log_error("SearchPathW failed: %s\n", get_last_error_str());
goto cleanup_exec;
}
command_path_w.resize(command_path_len_w - 1);
@ -448,19 +448,19 @@ struct RpcFrontend : public Pass {
pipe_attr.bInheritHandle = TRUE;
pipe_attr.lpSecurityDescriptor = NULL;
if (!CreatePipe(&send_r, &send_w, &pipe_attr, /*nSize=*/0)) {
log_error("CreatePipe failed: %s\n", get_last_error_str().c_str());
log_error("CreatePipe failed: %s\n", get_last_error_str());
goto cleanup_exec;
}
if (!SetHandleInformation(send_w, HANDLE_FLAG_INHERIT, 0)) {
log_error("SetHandleInformation failed: %s\n", get_last_error_str().c_str());
log_error("SetHandleInformation failed: %s\n", get_last_error_str());
goto cleanup_exec;
}
if (!CreatePipe(&recv_r, &recv_w, &pipe_attr, /*nSize=*/0)) {
log_error("CreatePipe failed: %s\n", get_last_error_str().c_str());
log_error("CreatePipe failed: %s\n", get_last_error_str());
goto cleanup_exec;
}
if (!SetHandleInformation(recv_r, HANDLE_FLAG_INHERIT, 0)) {
log_error("SetHandleInformation failed: %s\n", get_last_error_str().c_str());
log_error("SetHandleInformation failed: %s\n", get_last_error_str());
goto cleanup_exec;
}
@ -470,7 +470,7 @@ struct RpcFrontend : public Pass {
startup_info.hStdError = GetStdHandle(STD_ERROR_HANDLE);
startup_info.dwFlags |= STARTF_USESTDHANDLES;
if (!CreateProcessW(/*lpApplicationName=*/command_path_w.c_str(), /*lpCommandLine=*/&command_line_w[0], /*lpProcessAttributes=*/NULL, /*lpThreadAttributes=*/NULL, /*bInheritHandles=*/TRUE, /*dwCreationFlags=*/0, /*lpEnvironment=*/NULL, /*lpCurrentDirectory=*/NULL, &startup_info, &proc_info)) {
log_error("CreateProcessW failed: %s\n", get_last_error_str().c_str());
log_error("CreateProcessW failed: %s\n", get_last_error_str());
goto cleanup_exec;
}
CloseHandle(proc_info.hProcess);
@ -550,7 +550,7 @@ cleanup_exec:
h = CreateFileW(path_w.c_str(), GENERIC_READ|GENERIC_WRITE, /*dwShareMode=*/0, /*lpSecurityAttributes=*/NULL, /*dwCreationDisposition=*/OPEN_EXISTING, /*dwFlagsAndAttributes=*/0, /*hTemplateFile=*/NULL);
if (h == INVALID_HANDLE_VALUE) {
log_error("CreateFileW failed: %s\n", get_last_error_str().c_str());
log_error("CreateFileW failed: %s\n", get_last_error_str());
goto cleanup_path;
}
@ -586,7 +586,7 @@ cleanup_path:
log_cmd_error("Failed to connect to RPC frontend.\n");
for (auto &module_name : server->get_module_names()) {
log("Linking module `%s'.\n", module_name.c_str());
log("Linking module `%s'.\n", module_name);
RpcModule *module = new RpcModule;
module->name = "$abstract\\" + module_name;
module->server = server;

2
frontends/rtlil/rtlil_frontend.cc
View file

@ -90,7 +90,7 @@ struct RTLILFrontend : public Frontend {
}
extra_args(f, filename, args, argidx);
log("Input filename: %s\n", filename.c_str());
log("Input filename: %s\n", filename);
RTLIL_FRONTEND::lexin = f;
RTLIL_FRONTEND::current_design = design;

24
frontends/verific/verific.cc
View file

@ -156,7 +156,7 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil
if (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_WARNING || msg_type == VERIFIC_PROGRAM_ERROR)
log_warning_noprefix("%s%s\n", message_prefix.c_str(), message.c_str());
else
log("%s%s\n", message_prefix.c_str(), message.c_str());
log("%s%s\n", message_prefix, message);
}
if (verific_error_msg.empty() && (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_PROGRAM_ERROR))
verific_error_msg = message;
@ -267,7 +267,7 @@ static const RTLIL::Const extract_vhdl_bit(std::string &val, std::string &typ)
{
if (val.size()==3 && val[0]=='\'' && val.back()=='\'')
return RTLIL::Const::from_string(val.substr(1,val.size()-2));
log_error("Error parsing VHDL %s.\n", typ.c_str());
log_error("Error parsing VHDL %s.\n", typ);
}
static const RTLIL::Const extract_vhdl_bit_vector(std::string &val, std::string &typ)
@ -278,7 +278,7 @@ static const RTLIL::Const extract_vhdl_bit_vector(std::string &val, std::string
c.flags |= RTLIL::CONST_FLAG_SIGNED;
return c;
}
log_error("Error parsing VHDL %s.\n", typ.c_str());
log_error("Error parsing VHDL %s.\n", typ);
}
static const RTLIL::Const extract_vhdl_integer(std::string &val)
@ -2726,7 +2726,7 @@ struct VerificExtNets
cursor = ((Instance*)cursor->GetReferences()->GetLast())->Owner();
}
log_error("No common ancestor found between %s and %s.\n", get_full_netlist_name(A).c_str(), get_full_netlist_name(B).c_str());
log_error("No common ancestor found between %s and %s.\n", get_full_netlist_name(A), get_full_netlist_name(B));
}
void run(Netlist *nl)
@ -2750,17 +2750,17 @@ struct VerificExtNets
continue;
if (verific_verbose)
log("Fixing external net reference on port %s.%s.%s:\n", get_full_netlist_name(nl).c_str(), inst->Name(), port->Name());
log("Fixing external net reference on port %s.%s.%s:\n", get_full_netlist_name(nl), inst->Name(), port->Name());
Netlist *ext_nl = net->Owner();
if (verific_verbose)
log(" external net owner: %s\n", get_full_netlist_name(ext_nl).c_str());
log(" external net owner: %s\n", get_full_netlist_name(ext_nl));
Netlist *ca_nl = find_common_ancestor(nl, ext_nl);
if (verific_verbose)
log(" common ancestor: %s\n", get_full_netlist_name(ca_nl).c_str());
log(" common ancestor: %s\n", get_full_netlist_name(ca_nl));
Net *ca_net = route_up(net, !port->IsOutput(), ca_nl);
Net *new_net = ca_net;
@ -3128,7 +3128,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
#endif
if (!verific_error_msg.empty())
log_error("%s\n", verific_error_msg.c_str());
log_error("%s\n", verific_error_msg);
if (!verific_no_split_complex_ports)
for (auto nl : nl_todo)
@ -3166,7 +3166,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
verific_cleanup();
if (!verific_error_msg.empty())
log_error("%s\n", verific_error_msg.c_str());
log_error("%s\n", verific_error_msg);
return top;
}
@ -3455,7 +3455,7 @@ struct VerificPass : public Pass {
char block[4096];
while (1) {
if (fgets(block, 4096, Frontend::current_script_file == nullptr? stdin : Frontend::current_script_file) == nullptr)
log_error("Unexpected end of file in here document '%s'!\n", filename.c_str());
log_error("Unexpected end of file in here document '%s'!\n", filename);
buffer += block;
if (buffer.size() > 0 && (buffer[buffer.size() - 1] == '\n' || buffer[buffer.size() - 1] == '\r'))
break;
@ -4460,7 +4460,7 @@ struct VerificPass : public Pass {
}
lines.sort();
for (auto &line : lines)
log("verific -cfg %s\n", line.c_str());
log("verific -cfg %s\n", line);
goto check_error;
}
@ -4519,7 +4519,7 @@ struct VerificPass : public Pass {
}
if (!verific_error_msg.empty())
log_error("%s\n", verific_error_msg.c_str());
log_error("%s\n", verific_error_msg);
}
#else /* YOSYS_ENABLE_VERIFIC */

2
frontends/verific/verificsva.cc
View file

@ -1024,7 +1024,7 @@ struct VerificSvaImporter
[[noreturn]] void parser_error(std::string errmsg)
{
if (!importer->mode_keep)
log_error("%s", errmsg.c_str());
log_error("%s", errmsg);
log_warning("%s", errmsg.c_str());
throw ParserErrorException();
}

8
frontends/verilog/preproc.cc
View file

@ -242,7 +242,7 @@ struct arg_map_t
void add_arg(const std::string &name, const char *default_value)
{
if (find(name)) {
log_error("Duplicate macro arguments with name `%s'.\n", name.c_str());
log_error("Duplicate macro arguments with name `%s'.\n", name);
}
name_to_pos[name] = args.size();
@ -789,14 +789,14 @@ frontend_verilog_preproc(std::istream &f,
else if (ifdef_pass_level > 0)
ifdef_pass_level--;
else
log_error("Found %s outside of macro conditional branch!\n", tok.c_str());
log_error("Found %s outside of macro conditional branch!\n", tok);
continue;
}
if (tok == "`else") {
if (ifdef_fail_level == 0) {
if (ifdef_pass_level == 0)
log_error("Found %s outside of macro conditional branch!\n", tok.c_str());
log_error("Found %s outside of macro conditional branch!\n", tok);
ifdef_pass_level--;
ifdef_fail_level = 1;
ifdef_already_satisfied = true;
@ -813,7 +813,7 @@ frontend_verilog_preproc(std::istream &f,
std::string name = next_token(true);
if (ifdef_fail_level == 0) {
if (ifdef_pass_level == 0)
log_error("Found %s outside of macro conditional branch!\n", tok.c_str());
log_error("Found %s outside of macro conditional branch!\n", tok);
ifdef_pass_level--;
ifdef_fail_level = 1;
ifdef_already_satisfied = true;

35
frontends/verilog/verilog_error.cc
View file

@ -32,37 +32,14 @@ USING_YOSYS_NAMESPACE
*/
[[noreturn]]
static void verr_at(std::string filename, int begin_line, char const *fmt, va_list ap)
void VERILOG_FRONTEND::formatted_err_at_loc(Location loc, std::string str)
{
char buffer[1024];
char *p = buffer;
p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap);
p += snprintf(p, buffer + sizeof(buffer) - p, "\n");
YOSYS_NAMESPACE_PREFIX log_file_error(filename, begin_line, "%s", buffer);
exit(1);
YOSYS_NAMESPACE_PREFIX log_file_error(loc.begin.filename ? *(loc.begin.filename) : "UNKNOWN", loc.begin.line,
"%s\n", std::move(str));
}
static void vwarn_at(std::string filename, int begin_line, char const *fmt, va_list ap)
void VERILOG_FRONTEND::formatted_warn_at_loc(Location loc, std::string str)
{
char buffer[1024];
char *p = buffer;
p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap);
p += snprintf(p, buffer + sizeof(buffer) - p, "\n");
YOSYS_NAMESPACE_PREFIX log_file_warning(filename, begin_line, "%s", buffer);
YOSYS_NAMESPACE_PREFIX log_file_warning(loc.begin.filename ? *(loc.begin.filename) : "UNKNOWN", loc.begin.line,
"%s\n", std::move(str));
}
[[noreturn]]
void VERILOG_FRONTEND::err_at_loc(Location loc, char const *fmt, ...)
{
va_list args;
va_start(args, fmt);
verr_at(loc.begin.filename ? *(loc.begin.filename) : "UNKNOWN", loc.begin.line, fmt, args);
}
void VERILOG_FRONTEND::warn_at_loc(Location loc, char const *fmt, ...)
{
va_list args;
va_start(args, fmt);
vwarn_at(loc.begin.filename ? *(loc.begin.filename) : "UNKNOWN", loc.begin.line, fmt, args);
va_end(args);
}

16
frontends/verilog/verilog_error.h
View file

@ -10,8 +10,20 @@ YOSYS_NAMESPACE_BEGIN
namespace VERILOG_FRONTEND
{
[[noreturn]]
void err_at_loc(Location loc, char const *fmt, ...);
void warn_at_loc(Location loc, char const *fmt, ...);
void formatted_err_at_loc(Location loc, std::string str);
template <typename... Args>
[[noreturn]]
void err_at_loc(Location loc, FmtString<TypeIdentity<Args>...> fmt, const Args &... args)
{
formatted_err_at_loc(std::move(loc), fmt.format(args...));
}
void formatted_warn_at_loc(Location loc, std::string str);
template <typename... Args>
void warn_at_loc(Location loc, FmtString<TypeIdentity<Args>...> fmt, const Args &... args)
{
formatted_warn_at_loc(std::move(loc), fmt.format(args...));
}
};
YOSYS_NAMESPACE_END

4
frontends/verilog/verilog_frontend.cc
View file

@ -51,7 +51,7 @@ static std::list<std::vector<std::string>> verilog_defaults_stack;
static void error_on_dpi_function(AST::AstNode *node)
{
if (node->type == AST::AST_DPI_FUNCTION)
err_at_loc(node->location, "Found DPI function %s.\n", node->str.c_str());
err_at_loc(node->location, "Found DPI function %s.\n", node->str);
for (auto& child : node->children)
error_on_dpi_function(child.get());
}
@ -497,7 +497,7 @@ struct VerilogFrontend : public Frontend {
if (!flag_nopp) {
code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, *design->verilog_defines, include_dirs, parse_state, parse_mode);
if (flag_ppdump)
log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc.c_str());
log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc);
parse_state.lexin = new std::istringstream(code_after_preproc);
}

328
frontends/verilog/verilog_parser.y
View file

@ -69,9 +69,10 @@
struct ParseState {
int port_counter;
dict<std::string, int> port_stubs;
dict<IdString, std::unique_ptr<AstNode>> *attr_list, default_attr_list;
std::stack<dict<IdString, std::unique_ptr<AstNode>> *> attr_list_stack;
dict<IdString, std::unique_ptr<AstNode>> *albuf;
std::unique_ptr<dict<IdString, std::unique_ptr<AstNode>>> attr_list;
dict<IdString, std::unique_ptr<AstNode>> default_attr_list;
std::stack<std::unique_ptr<dict<IdString, std::unique_ptr<AstNode>>>> attr_list_stack;
std::unique_ptr<dict<IdString, std::unique_ptr<AstNode>>> albuf;
std::vector<UserTypeMap> user_type_stack;
dict<std::string, AstNode*> pkg_user_types;
std::vector<AstNode*> ast_stack;
@ -97,13 +98,16 @@
bool isInLocalScope(const std::string *name);
void rewriteGenForDeclInit(AstNode *loop);
void ensureAsgnExprAllowed(const parser::location_type loc, bool sv_mode);
const AstNode *addIncOrDecStmt(dict<IdString, std::unique_ptr<AstNode>> *stmt_attr,
const AstNode *addIncOrDecStmt(std::unique_ptr<dict<IdString, std::unique_ptr<AstNode>>> stmt_attr,
std::unique_ptr<AstNode> lhs,
dict<IdString, std::unique_ptr<AstNode>> *op_attr, AST::AstNodeType op,
std::unique_ptr<dict<IdString, std::unique_ptr<AstNode>>> op_attr, AST::AstNodeType op,
parser::location_type loc);
std::unique_ptr<AstNode> addIncOrDecExpr(std::unique_ptr<AstNode> lhs, dict<IdString, std::unique_ptr<AstNode>> *attr, AST::AstNodeType op, parser::location_type loc, bool undo, bool sv_mode);
std::unique_ptr<AstNode> addIncOrDecExpr(std::unique_ptr<AstNode> lhs,
std::unique_ptr<dict<IdString, std::unique_ptr<AstNode>>> attr,
AST::AstNodeType op, parser::location_type loc, bool undo, bool sv_mode);
// add a binary operator assignment statement, e.g., a += b
std::unique_ptr<AstNode> addAsgnBinopStmt(dict<IdString, std::unique_ptr<AstNode>> *attr, std::unique_ptr<AstNode> eq_lhs, AST::AstNodeType op, std::unique_ptr<AstNode> rhs);
std::unique_ptr<AstNode> addAsgnBinopStmt(std::unique_ptr<dict<IdString, std::unique_ptr<AstNode>>> attr,
std::unique_ptr<AstNode> eq_lhs, AST::AstNodeType op, std::unique_ptr<AstNode> rhs);
};
struct ParseMode {
bool noassert = false;
@ -150,26 +154,20 @@
return Location(begin.begin, end.end);
}
static void append_attr(AstNode *ast, dict<IdString, std::unique_ptr<AstNode>> *al)
static void append_attr(AstNode *ast, std::unique_ptr<dict<IdString, std::unique_ptr<AstNode>>> al)
{
for (auto &it : *al) {
ast->attributes[it.first] = std::move(it.second);
}
delete al;
}
static void append_attr_clone(AstNode *ast, dict<IdString, std::unique_ptr<AstNode>> *al)
static void append_attr_clone(AstNode *ast, std::unique_ptr<dict<IdString, std::unique_ptr<AstNode>>> &al)
{
for (auto &it : *al) {
ast->attributes[it.first] = it.second->clone();
}
}
static void free_attr(dict<IdString, std::unique_ptr<AstNode>> *al)
{
delete al;
}
static std::unique_ptr<AstNode> makeRange(parser::location_type loc, int msb = 31, int lsb = 0, bool isSigned = true)
{
auto range = std::make_unique<AstNode>(loc, AST_RANGE);
@ -363,28 +361,31 @@
}
// add a pre/post-increment/decrement statement
const AstNode *ParseState::addIncOrDecStmt(dict<IdString, std::unique_ptr<AstNode>> *stmt_attr,
const AstNode *ParseState::addIncOrDecStmt(std::unique_ptr<dict<IdString, std::unique_ptr<AstNode>>> stmt_attr,
std::unique_ptr<AstNode> lhs,
dict<IdString, std::unique_ptr<AstNode>> *op_attr, AST::AstNodeType op,
std::unique_ptr<dict<IdString, std::unique_ptr<AstNode>>> op_attr, AST::AstNodeType op,
Location loc)
{
auto one = AstNode::mkconst_int(loc, 1, true);
auto rhs = std::make_unique<AstNode>(loc, op, lhs->clone(), std::move(one));
if (op_attr != nullptr)
append_attr(rhs.get(), op_attr);
if (op_attr)
append_attr(rhs.get(), std::move(op_attr));
auto stmt_owned = std::make_unique<AstNode>(loc, AST_ASSIGN_EQ, std::move(lhs), std::move(rhs));
auto* stmt = stmt_owned.get();
ast_stack.back()->children.push_back(std::move(stmt_owned));
if (stmt_attr != nullptr)
append_attr(stmt, stmt_attr);
if (stmt_attr)
append_attr(stmt, std::move(stmt_attr));
return stmt;
}
// create a pre/post-increment/decrement expression, and add the corresponding statement
std::unique_ptr<AstNode> ParseState::addIncOrDecExpr(std::unique_ptr<AstNode> lhs, dict<IdString, std::unique_ptr<AstNode>> *attr, AST::AstNodeType op, Location loc, bool undo, bool sv_mode)
std::unique_ptr<AstNode> ParseState::addIncOrDecExpr(std::unique_ptr<AstNode> lhs,
std::unique_ptr<dict<IdString,
std::unique_ptr<AstNode>>> attr,
AST::AstNodeType op, Location loc, bool undo, bool sv_mode)
{
ensureAsgnExprAllowed(loc, sv_mode);
const AstNode *stmt = addIncOrDecStmt(nullptr, std::move(lhs), attr, op, loc);
const AstNode *stmt = addIncOrDecStmt(nullptr, std::move(lhs), std::move(attr), op, loc);
log_assert(stmt->type == AST_ASSIGN_EQ);
auto expr = stmt->children[0]->clone();
if (undo) {
@ -396,7 +397,8 @@
}
// add a binary operator assignment statement, e.g., a += b
std::unique_ptr<AstNode> ParseState::addAsgnBinopStmt(dict<IdString, std::unique_ptr<AstNode>> *attr, std::unique_ptr<AstNode> eq_lhs, AST::AstNodeType op, std::unique_ptr<AstNode> rhs)
std::unique_ptr<AstNode> ParseState::addAsgnBinopStmt(std::unique_ptr<dict<IdString, std::unique_ptr<AstNode>>> attr,
std::unique_ptr<AstNode> eq_lhs, AST::AstNodeType op, std::unique_ptr<AstNode> rhs)
{
Location loc = location_range(eq_lhs->location, rhs->location);
if (op == AST_SHIFT_LEFT || op == AST_SHIFT_RIGHT ||
@ -409,8 +411,8 @@
auto stmt_owned = std::make_unique<AstNode>(loc, AST_ASSIGN_EQ, std::move(eq_lhs), std::move(eq_rhs_owned));
auto* stmt = stmt_owned.get();
ast_stack.back()->children.push_back(std::move(stmt_owned));
if (attr != nullptr)
append_attr(stmt, attr);
if (attr)
append_attr(stmt, std::move(attr));
return ret_lhs;
}
};
@ -418,7 +420,7 @@
void frontend_verilog_yy::parser::error(const frontend_verilog_yy::parser::location_type& loc, const std::string& msg)
{
err_at_loc(loc, "%s", msg.c_str());
err_at_loc(loc, "%s", msg);
}
}
@ -460,7 +462,7 @@
using string_t = std::unique_ptr<std::string>;
using ast_t = std::unique_ptr<YOSYS_NAMESPACE_PREFIX AST::AstNode>;
using al_t = YOSYS_NAMESPACE_PREFIX dict<YOSYS_NAMESPACE_PREFIX RTLIL::IdString, std::unique_ptr<YOSYS_NAMESPACE_PREFIX AST::AstNode>>*;
using al_t = std::unique_ptr<YOSYS_NAMESPACE_PREFIX dict<YOSYS_NAMESPACE_PREFIX RTLIL::IdString, std::unique_ptr<YOSYS_NAMESPACE_PREFIX AST::AstNode>>>;
using specify_target_ptr_t = std::unique_ptr<struct specify_target>;
using specify_triple_ptr_t = std::unique_ptr<struct specify_triple>;
using specify_rise_fall_ptr_t = std::unique_ptr<struct specify_rise_fall>;
@ -613,15 +615,15 @@ design:
attr:
{
if (extra->attr_list != nullptr)
extra->attr_list_stack.push(extra->attr_list);
extra->attr_list = new dict<IdString, std::unique_ptr<AstNode>>;
if (extra->attr_list)
extra->attr_list_stack.push(std::move(extra->attr_list));
extra->attr_list = std::make_unique<dict<IdString, std::unique_ptr<AstNode>>>();
for (auto &it : extra->default_attr_list)
(*extra->attr_list)[it.first] = it.second->clone();
} attr_opt {
$$ = extra->attr_list;
$$ = std::move(extra->attr_list);
if (!extra->attr_list_stack.empty()) {
extra->attr_list = extra->attr_list_stack.top();
extra->attr_list = std::move(extra->attr_list_stack.top());
extra->attr_list_stack.pop();
} else
extra->attr_list = nullptr;
@ -636,14 +638,14 @@ attr_opt:
defattr:
DEFATTR_BEGIN {
if (extra->attr_list != nullptr)
extra->attr_list_stack.push(extra->attr_list);
extra->attr_list = new dict<IdString, std::unique_ptr<AstNode>>;
extra->attr_list_stack.push(std::move(extra->attr_list));
extra->attr_list = std::make_unique<dict<IdString, std::unique_ptr<AstNode>>>();
extra->default_attr_list.clear();
} opt_attr_list {
extra->attr_list->swap(extra->default_attr_list);
delete extra->attr_list;
extra->attr_list.reset();
if (!extra->attr_list_stack.empty()) {
extra->attr_list = extra->attr_list_stack.top();
extra->attr_list = std::move(extra->attr_list_stack.top());
extra->attr_list_stack.pop();
} else
extra->attr_list = nullptr;
@ -699,7 +701,7 @@ module:
extra->port_stubs.clear();
extra->port_counter = 0;
mod->str = *$4;
append_attr(mod, $1);
append_attr(mod, std::move($1));
} module_para_opt module_args_opt TOK_SEMICOL module_body TOK_ENDMODULE opt_label {
if (extra->port_stubs.size() != 0)
err_at_loc(@7, "Missing details for module port `%s'.",
@ -723,12 +725,12 @@ single_module_para:
attr TOK_PARAMETER {
extra->astbuf1 = std::make_unique<AstNode>(@$, AST_PARAMETER);
extra->astbuf1->children.push_back(AstNode::mkconst_int(@2, 0, true));
append_attr(extra->astbuf1.get(), $1);
append_attr(extra->astbuf1.get(), std::move($1));
} param_type single_param_decl |
attr TOK_LOCALPARAM {
extra->astbuf1 = std::make_unique<AstNode>(@$, AST_LOCALPARAM);
extra->astbuf1->children.push_back(AstNode::mkconst_int(@2, 0, true));
append_attr(extra->astbuf1.get(), $1);
append_attr(extra->astbuf1.get(), std::move($1));
} param_type single_param_decl |
single_param_decl;
@ -770,7 +772,7 @@ module_arg:
extra->ast_stack.back()->children.push_back(std::move(node));
} else {
if (extra->port_stubs.count(*$1) != 0)
err_at_loc(@1, "Duplicate module port `%s'.", $1->c_str());
err_at_loc(@1, "Duplicate module port `%s'.", *$1);
extra->port_stubs[*$1] = ++extra->port_counter;
}
} module_arg_opt_assignment |
@ -780,7 +782,7 @@ module_arg:
extra->astbuf1->children[0]->str = *$1;
} TOK_ID { /* SV interfaces */
if (!mode->sv)
err_at_loc(@3, "Interface found in port list (%s). This is not supported unless read_verilog is called with -sv!", $3->c_str());
err_at_loc(@3, "Interface found in port list (%s). This is not supported unless read_verilog is called with -sv!", *$3);
extra->astbuf2 = extra->astbuf1->clone(); // really only needed if multiple instances of same type.
extra->astbuf2->str = *$3;
extra->astbuf2->port_id = ++extra->port_counter;
@ -795,10 +797,10 @@ module_arg:
if (range != nullptr)
node->children.push_back(std::move(range));
if (!node->is_input && !node->is_output)
err_at_loc(@4, "Module port `%s' is neither input nor output.", $4->c_str());
err_at_loc(@4, "Module port `%s' is neither input nor output.", *$4);
if (node->is_reg && node->is_input && !node->is_output && !mode->sv)
err_at_loc(@4, "Input port `%s' is declared as register.", $4->c_str());
append_attr(node.get(), $1);
err_at_loc(@4, "Input port `%s' is declared as register.", *$4);
append_attr(node.get(), std::move($1));
extra->ast_stack.back()->children.push_back(std::move(node));
} module_arg_opt_assignment |
TOK_DOT TOK_DOT TOK_DOT {
@ -812,7 +814,7 @@ package:
AstNode* mod = extra->pushChild(std::make_unique<AstNode>(@$, AST_PACKAGE));
extra->current_ast_mod = mod;
mod->str = *$4;
append_attr(mod, $1);
append_attr(mod, std::move($1));
} TOK_SEMICOL package_body TOK_ENDPACKAGE opt_label {
extra->ast_stack.pop_back();
checkLabelsMatch(@9, "Package name", $4.get(), $9.get());
@ -1114,28 +1116,28 @@ task_func_decl:
attr TOK_DPI_FUNCTION TOK_ID TOK_ID {
extra->current_function_or_task = extra->saveChild(std::make_unique<AstNode>(@$, AST_DPI_FUNCTION, AstNode::mkconst_str(@3, *$3), AstNode::mkconst_str(@4, *$4)));
extra->current_function_or_task->str = *$4;
append_attr(extra->current_function_or_task, $1);
append_attr(extra->current_function_or_task, std::move($1));
} opt_dpi_function_args TOK_SEMICOL {
extra->current_function_or_task = nullptr;
} |
attr TOK_DPI_FUNCTION TOK_ID TOK_EQ TOK_ID TOK_ID {
extra->current_function_or_task = extra->saveChild(std::make_unique<AstNode>(@$, AST_DPI_FUNCTION, AstNode::mkconst_str(@5, *$5), AstNode::mkconst_str(@3, *$3)));
extra->current_function_or_task->str = *$6;
append_attr(extra->current_function_or_task, $1);
append_attr(extra->current_function_or_task, std::move($1));
} opt_dpi_function_args TOK_SEMICOL {
extra->current_function_or_task = nullptr;
} |
attr TOK_DPI_FUNCTION TOK_ID TOK_COL TOK_ID TOK_EQ TOK_ID TOK_ID {
extra->current_function_or_task = extra->saveChild(std::make_unique<AstNode>(@$, AST_DPI_FUNCTION, AstNode::mkconst_str(@7, *$7), AstNode::mkconst_str(location_range(@3, @5), *$3 + ":" + RTLIL::unescape_id(*$5))));
extra->current_function_or_task->str = *$8;
append_attr(extra->current_function_or_task, $1);
append_attr(extra->current_function_or_task, std::move($1));
} opt_dpi_function_args TOK_SEMICOL {
extra->current_function_or_task = nullptr;
} |
attr TOK_TASK opt_automatic TOK_ID {
extra->current_function_or_task = extra->pushChild(std::make_unique<AstNode>(@$, AST_TASK));
extra->current_function_or_task->str = *$4;
append_attr(extra->current_function_or_task, $1);
append_attr(extra->current_function_or_task, std::move($1));
extra->current_function_or_task_port_id = 1;
} task_func_args_opt TOK_SEMICOL task_func_body TOK_ENDTASK {
extra->current_function_or_task = nullptr;
@ -1149,7 +1151,7 @@ task_func_decl:
// function like a task.
extra->current_function_or_task = extra->pushChild(std::make_unique<AstNode>(@$, AST_TASK));
extra->current_function_or_task->str = *$5;
append_attr(extra->current_function_or_task, $1);
append_attr(extra->current_function_or_task, std::move($1));
extra->current_function_or_task_port_id = 1;
} task_func_args_opt TOK_SEMICOL task_func_body TOK_ENDFUNCTION {
extra->current_function_or_task = nullptr;
@ -1158,7 +1160,7 @@ task_func_decl:
attr TOK_FUNCTION opt_automatic func_return_type TOK_ID {
extra->current_function_or_task = extra->pushChild(std::make_unique<AstNode>(@$, AST_FUNCTION));
extra->current_function_or_task->str = *$5;
append_attr(extra->current_function_or_task, $1);
append_attr(extra->current_function_or_task, std::move($1));
auto outreg = std::make_unique<AstNode>(@$, AST_WIRE);
outreg->str = *$5;
outreg->is_signed = false;
@ -1240,7 +1242,7 @@ task_func_args_opt:
(void)extra->astbuf1.reset();
if (extra->astbuf2 != nullptr)
(void)extra->astbuf2.reset();
free_attr(extra->albuf);
extra->albuf.reset();
} TOK_RPAREN;
task_func_args:
@ -1256,9 +1258,9 @@ task_func_port:
(void)extra->astbuf1.reset();
if (extra->astbuf2 != nullptr)
(void)extra->astbuf2.reset();
free_attr(extra->albuf);
extra->albuf.reset();
}
extra->albuf = $1;
extra->albuf = std::move($1);
extra->astbuf1 = std::move($2);
extra->astbuf2 = checkRange(extra->astbuf1.get(), std::move($3));
if (!extra->astbuf1->is_input && !extra->astbuf1->is_output) {
@ -1272,7 +1274,7 @@ task_func_port:
if (!extra->astbuf1) {
if (!mode->sv)
err_at_loc(@$, "task/function argument direction missing");
extra->albuf = new dict<IdString, std::unique_ptr<AstNode>>;
extra->albuf = std::make_unique<dict<IdString, std::unique_ptr<AstNode>>>();
extra->astbuf1 = std::make_unique<AstNode>(@$, AST_WIRE);
extra->current_wire_rand = false;
extra->current_wire_const = false;
@ -1379,7 +1381,7 @@ specify_item:
TOK_ID TOK_LPAREN specify_edge expr specify_condition TOK_COMMA specify_edge expr specify_condition TOK_COMMA specify_triple specify_opt_triple TOK_RPAREN TOK_SEMICOL {
if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$setuphold" && *$1 != "$removal" && *$1 != "$recovery" &&
*$1 != "$recrem" && *$1 != "$skew" && *$1 != "$timeskew" && *$1 != "$fullskew" && *$1 != "$nochange")
err_at_loc(@1, "Unsupported specify rule type: %s", $1->c_str());
err_at_loc(@1, "Unsupported specify rule type: %s", *$1);
auto src_pen = AstNode::mkconst_int(@3, $3 != 0, false, 1);
auto src_pol = AstNode::mkconst_int(@3, $3 == 'p', false, 1);
@ -1601,23 +1603,23 @@ state_dependent_path_declaration:
module_path_expression:
module_path_primary
// Flatten out unary_operator to avoid shift/reduce conflict
| TOK_EXCL attr module_path_primary { free_attr($2); }
| TOK_TILDE attr module_path_primary { free_attr($2); }
| TOK_AMP attr module_path_primary { free_attr($2); }
| OP_NAND attr module_path_primary { free_attr($2); }
| TOK_PIPE attr module_path_primary { free_attr($2); }
| OP_NOR attr module_path_primary { free_attr($2); }
| TOK_CARET attr module_path_primary { free_attr($2); }
| OP_XNOR attr module_path_primary { free_attr($2); }
| TOK_EXCL attr module_path_primary
| TOK_TILDE attr module_path_primary
| TOK_AMP attr module_path_primary
| OP_NAND attr module_path_primary
| TOK_PIPE attr module_path_primary
| OP_NOR attr module_path_primary
| TOK_CARET attr module_path_primary
| OP_XNOR attr module_path_primary
// Flatten out binary_operator to avoid shift/reduce conflict
| module_path_expression OP_EQ attr module_path_expression { free_attr($3); }
| module_path_expression OP_NE attr module_path_expression { free_attr($3); }
| module_path_expression OP_LAND attr module_path_expression { free_attr($3); }
| module_path_expression OP_LOR attr module_path_expression { free_attr($3); }
| module_path_expression TOK_AMP attr module_path_expression { free_attr($3); }
| module_path_expression TOK_PIPE attr module_path_expression { free_attr($3); }
| module_path_expression TOK_CARET attr module_path_expression { free_attr($3); }
| module_path_expression OP_XNOR attr module_path_expression { free_attr($3); }
| module_path_expression OP_EQ attr module_path_expression
| module_path_expression OP_NE attr module_path_expression
| module_path_expression OP_LAND attr module_path_expression
| module_path_expression OP_LOR attr module_path_expression
| module_path_expression TOK_AMP attr module_path_expression
| module_path_expression TOK_PIPE attr module_path_expression
| module_path_expression TOK_CARET attr module_path_expression
| module_path_expression OP_XNOR attr module_path_expression
// | module_path_conditional_expression
;
@ -1760,7 +1762,7 @@ param_decl:
attr TOK_PARAMETER {
extra->astbuf1 = std::make_unique<AstNode>(@$, AST_PARAMETER);
extra->astbuf1->children.push_back(AstNode::mkconst_int(@$, 0, true));
append_attr(extra->astbuf1.get(), $1);
append_attr(extra->astbuf1.get(), std::move($1));
} param_type param_decl_list TOK_SEMICOL {
(void)extra->astbuf1.reset();
};
@ -1769,7 +1771,7 @@ localparam_decl:
attr TOK_LOCALPARAM {
extra->astbuf1 = std::make_unique<AstNode>(@$, AST_LOCALPARAM);
extra->astbuf1->children.push_back(AstNode::mkconst_int(@$, 0, true));
append_attr(extra->astbuf1.get(), $1);
append_attr(extra->astbuf1.get(), std::move($1));
} param_type param_decl_list TOK_SEMICOL {
(void)extra->astbuf1.reset();
};
@ -1925,7 +1927,7 @@ enum_decl: enum_type enum_var_list TOK_SEMICOL { }
struct_decl:
attr struct_type {
append_attr(extra->astbuf2.get(), $1);
append_attr(extra->astbuf2.get(), std::move($1));
} struct_var_list TOK_SEMICOL {
(void)extra->astbuf2.reset();
}
@ -2031,26 +2033,26 @@ struct_var:
wire_decl:
attr wire_type range_or_multirange {
extra->albuf = $1;
extra->albuf = std::move($1);
extra->astbuf1 = std::move($2);
extra->astbuf2 = checkRange(extra->astbuf1.get(), std::move($3));
} delay wire_name_list {
(void)extra->astbuf1.reset();
if (extra->astbuf2 != nullptr)
(void)extra->astbuf2.reset();
free_attr(extra->albuf);
extra->albuf.reset();
} TOK_SEMICOL |
attr TOK_SUPPLY0 TOK_ID {
extra->ast_stack.back()->children.push_back(std::make_unique<AstNode>(@$, AST_WIRE));
extra->ast_stack.back()->children.back()->str = *$3;
append_attr(extra->ast_stack.back()->children.back().get(), $1);
append_attr(extra->ast_stack.back()->children.back().get(), std::move($1));
extra->ast_stack.back()->children.push_back(std::make_unique<AstNode>(@$, AST_ASSIGN, std::make_unique<AstNode>(@$, AST_IDENTIFIER), AstNode::mkconst_int(@$, 0, false, 1)));
extra->ast_stack.back()->children.back()->children[0]->str = *$3;
} opt_supply_wires TOK_SEMICOL |
attr TOK_SUPPLY1 TOK_ID {
extra->ast_stack.back()->children.push_back(std::make_unique<AstNode>(@$, AST_WIRE));
extra->ast_stack.back()->children.back()->str = *$3;
append_attr(extra->ast_stack.back()->children.back().get(), $1);
append_attr(extra->ast_stack.back()->children.back().get(), std::move($1));
extra->ast_stack.back()->children.push_back(std::make_unique<AstNode>(@$, AST_ASSIGN, std::make_unique<AstNode>(@$, AST_IDENTIFIER), AstNode::mkconst_int(@$, 1, false, 1)));
extra->ast_stack.back()->children.back()->children[0]->str = *$3;
} opt_supply_wires TOK_SEMICOL;
@ -2154,21 +2156,21 @@ wire_name:
node->port_id = extra->current_function_or_task_port_id++;
} else if (extra->ast_stack.back()->type == AST_GENBLOCK) {
if (node->is_input || node->is_output)
err_at_loc(@1, "Cannot declare module port `%s' within a generate block.", $1->c_str());
err_at_loc(@1, "Cannot declare module port `%s' within a generate block.", *$1);
} else {
if (extra->do_not_require_port_stubs && (node->is_input || node->is_output) && extra->port_stubs.count(*$1) == 0) {
extra->port_stubs[*$1] = ++extra->port_counter;
}
if (extra->port_stubs.count(*$1) != 0) {
if (!node->is_input && !node->is_output)
err_at_loc(@1, "Module port `%s' is neither input nor output.", $1->c_str());
err_at_loc(@1, "Module port `%s' is neither input nor output.", *$1);
if (node->is_reg && node->is_input && !node->is_output && !mode->sv)
err_at_loc(@1, "Input port `%s' is declared as register.", $1->c_str());
err_at_loc(@1, "Input port `%s' is declared as register.", *$1);
node->port_id = extra->port_stubs[*$1];
extra->port_stubs.erase(*$1);
} else {
if (node->is_input || node->is_output)
err_at_loc(@1, "Module port `%s' is not declared in module header.", $1->c_str());
err_at_loc(@1, "Module port `%s' is not declared in module header.", *$1);
}
}
//FIXME: for some reason, TOK_ID has a location which always points to one column *after* the real last column...
@ -2243,7 +2245,7 @@ enum_struct_type:
cell_stmt:
attr TOK_ID {
extra->astbuf1 = std::make_unique<AstNode>(@$, AST_CELL);
append_attr(extra->astbuf1.get(), $1);
append_attr(extra->astbuf1.get(), std::move($1));
extra->astbuf1->children.push_back(std::make_unique<AstNode>(@$, AST_CELLTYPE));
extra->astbuf1->children[0]->str = *$2;
} cell_parameter_list_opt cell_list TOK_SEMICOL {
@ -2252,7 +2254,7 @@ cell_stmt:
attr tok_prim_wrapper delay {
extra->astbuf1 = std::make_unique<AstNode>(@$, AST_PRIMITIVE);
extra->astbuf1->str = *$2;
append_attr(extra->astbuf1.get(), $1);
append_attr(extra->astbuf1.get(), std::move($1));
} prim_list TOK_SEMICOL {
(void)extra->astbuf1.reset();
};
@ -2378,26 +2380,22 @@ cell_port:
attr {
auto node = std::make_unique<AstNode>(@$, AST_ARGUMENT);
extra->cell_hack->children.push_back(std::move(node));
free_attr($1);
} |
attr expr {
auto node = std::make_unique<AstNode>(@$, AST_ARGUMENT);
node->children.push_back(std::move($2));
extra->cell_hack->children.push_back(std::move(node));
free_attr($1);
} |
attr TOK_DOT TOK_ID TOK_LPAREN expr TOK_RPAREN {
auto node = std::make_unique<AstNode>(@$, AST_ARGUMENT);
node->str = *$3;
node->children.push_back(std::move($5));
extra->cell_hack->children.push_back(std::move(node));
free_attr($1);
} |
attr TOK_DOT TOK_ID TOK_LPAREN TOK_RPAREN {
auto node = std::make_unique<AstNode>(@$, AST_ARGUMENT);
node->str = *$3;
extra->cell_hack->children.push_back(std::move(node));
free_attr($1);
} |
attr TOK_DOT TOK_ID {
auto node = std::make_unique<AstNode>(@$, AST_ARGUMENT);
@ -2405,13 +2403,11 @@ cell_port:
node->children.push_back(std::make_unique<AstNode>(@$, AST_IDENTIFIER));
node->children.back()->str = *$3;
extra->cell_hack->children.push_back(std::move(node));
free_attr($1);
} |
attr TOK_WILDCARD_CONNECT {
if (!mode->sv)
err_at_loc(@2, "Wildcard port connections are only supported in SystemVerilog mode.");
extra->cell_hack->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(@2, 1, false);
free_attr($1);
};
always_comb_or_latch:
@ -2433,7 +2429,7 @@ always_or_always_ff:
always_stmt:
attr always_or_always_ff {
AstNode* node = extra->pushChild(std::make_unique<AstNode>(@$, AST_ALWAYS));
append_attr(node, $1);
append_attr(node, std::move($1));
if ($2)
node->attributes[ID::always_ff] = AstNode::mkconst_int(@2, 1, false);
} always_cond {
@ -2449,7 +2445,7 @@ always_stmt:
} |
attr always_comb_or_latch {
AstNode* node = extra->pushChild(std::make_unique<AstNode>(@$, AST_ALWAYS));
append_attr(node, $1);
append_attr(node, std::move($1));
if ($2)
node->attributes[ID::always_latch] = AstNode::mkconst_int(@2, 1, false);
else
@ -2461,7 +2457,7 @@ always_stmt:
} |
attr TOK_INITIAL {
AstNode* node = extra->pushChild(std::make_unique<AstNode>(@$, AST_INITIAL));
append_attr(node, $1);
append_attr(node, std::move($1));
(void)extra->pushChild(std::make_unique<AstNode>(@$, AST_BLOCK));
} behavioral_stmt {
extra->ast_stack.pop_back();
@ -2702,21 +2698,21 @@ simple_behavioral_stmt:
attr lvalue TOK_EQ delay expr {
AstNode* node = extra->saveChild(std::make_unique<AstNode>(@$, AST_ASSIGN_EQ, std::move($2), std::move($5)));
SET_AST_NODE_LOC(node, @2, @5);
append_attr(node, $1);
append_attr(node, std::move($1));
} |
attr lvalue attr inc_or_dec_op {
extra->addIncOrDecStmt($1, std::move($2), $3, $4, location_range(@1, @4));
extra->addIncOrDecStmt(std::move($1), std::move($2), std::move($3), $4, location_range(@1, @4));
} |
attr inc_or_dec_op attr lvalue {
extra->addIncOrDecStmt($1, std::move($4), $3, $2, location_range(@1, @4));
extra->addIncOrDecStmt(std::move($1), std::move($4), std::move($3), $2, location_range(@1, @4));
} |
attr lvalue OP_LE delay expr {
AstNode* node = extra->saveChild(std::make_unique<AstNode>(@$, AST_ASSIGN_LE, std::move($2), std::move($5)));
SET_AST_NODE_LOC(node, @2, @5);
append_attr(node, $1);
append_attr(node, std::move($1));
} |
attr lvalue asgn_binop delay expr {
(void)extra->addAsgnBinopStmt($1, std::move($2), $3, std::move($5));
(void)extra->addAsgnBinopStmt(std::move($1), std::move($2), $3, std::move($5));
};
asgn_binop:
@ -2790,13 +2786,11 @@ behavioral_stmt:
defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl |
non_opt_delay behavioral_stmt |
simple_behavioral_stmt TOK_SEMICOL |
attr TOK_SEMICOL {
free_attr($1);
} |
attr TOK_SEMICOL |
attr hierarchical_id {
AstNode* node = extra->pushChild(std::make_unique<AstNode>(@$, AST_TCALL));
node->str = *$2;
append_attr(node, $1);
append_attr(node, std::move($1));
} opt_arg_list TOK_SEMICOL{
SET_AST_NODE_LOC(extra->ast_stack.back(), @2, @5);
extra->ast_stack.pop_back();
@ -2804,7 +2798,7 @@ behavioral_stmt:
attr TOK_MSG_TASKS {
AstNode* node = extra->pushChild(std::make_unique<AstNode>(@$, AST_TCALL));
node->str = *$2;
append_attr(node, $1);
append_attr(node, std::move($1));
} opt_arg_list TOK_SEMICOL{
SET_AST_NODE_LOC(extra->ast_stack.back(), @2, @5);
extra->ast_stack.pop_back();
@ -2813,7 +2807,7 @@ behavioral_stmt:
extra->enterTypeScope();
} opt_label {
AstNode* node = extra->pushChild(std::make_unique<AstNode>(@$, AST_BLOCK));
append_attr(node, $1);
append_attr(node, std::move($1));
if ($4 != nullptr)
node->str = *$4;
} behavioral_stmt_list TOK_END opt_label {
@ -2834,7 +2828,7 @@ behavioral_stmt:
} |
attr TOK_FOR TOK_LPAREN {
AstNode* node = extra->pushChild(std::make_unique<AstNode>(@$, AST_FOR));
append_attr(node, $1);
append_attr(node, std::move($1));
} for_initialization TOK_SEMICOL expr {
extra->ast_stack.back()->children.push_back(std::move($7));
} TOK_SEMICOL simple_behavioral_stmt TOK_RPAREN {
@ -2848,7 +2842,7 @@ behavioral_stmt:
} |
attr TOK_WHILE TOK_LPAREN expr TOK_RPAREN {
AstNode* node = extra->pushChild(std::make_unique<AstNode>(@$, AST_WHILE));
append_attr(node, $1);
append_attr(node, std::move($1));
auto block_owned = std::make_unique<AstNode>(@$, AST_BLOCK);
auto* block = block_owned.get();
extra->ast_stack.back()->children.push_back(std::move($4));
@ -2861,7 +2855,7 @@ behavioral_stmt:
} |
attr TOK_REPEAT TOK_LPAREN expr TOK_RPAREN {
AstNode* node = extra->pushChild(std::make_unique<AstNode>(@$, AST_REPEAT));
append_attr(node, $1);
append_attr(node, std::move($1));
auto block_owned = std::make_unique<AstNode>(@$, AST_BLOCK);
auto* block = block_owned.get();
extra->ast_stack.back()->children.push_back(std::move($4));
@ -2896,11 +2890,9 @@ behavioral_stmt:
// not parallel "else if": begin new construction
node_owned = std::make_unique<AstNode>(@$, AST_CASE);
node = node_owned.get();
append_attr(node, $1);
append_attr(node, std::move($1));
node->children.push_back(node->get_bool_attribute(ID::parallel_case) ? AstNode::mkconst_int(@$, 1, false, 1) : expr->clone());
extra->ast_stack.back()->children.push_back(std::move(node_owned));
} else {
free_attr($1);
}
auto block_owned = std::make_unique<AstNode>(@$, AST_BLOCK);
auto* block = block_owned.get();
@ -2921,7 +2913,7 @@ behavioral_stmt:
} |
case_attr case_type TOK_LPAREN expr TOK_RPAREN {
AstNode* node = extra->pushChild(std::make_unique<AstNode>(@$, AST_CASE, std::move($4)));
append_attr(node, $1);
append_attr(node, std::move($1));
SET_AST_NODE_LOC(extra->ast_stack.back(), @4, @4);
} opt_synopsys_attr case_body TOK_ENDCASE {
SET_AST_NODE_LOC(extra->ast_stack.back(), @2, @9);
@ -2931,21 +2923,21 @@ behavioral_stmt:
if_attr:
attr {
$$ = $1;
$$ = std::move($1);
} |
attr TOK_UNIQUE0 {
AstNode *context = extra->ast_stack.back();
if (context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if))
err_at_loc(@2, "unique0 keyword cannot be used for 'else if' branch.");
(*$1)[ID::parallel_case] = AstNode::mkconst_int(@$, 1, false);
$$ = $1;
$$ = std::move($1);
} |
attr TOK_PRIORITY {
AstNode *context = extra->ast_stack.back();
if (context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if))
err_at_loc(@2, "priority keyword cannot be used for 'else if' branch.");
(*$1)[ID::full_case] = AstNode::mkconst_int(@$, 1, false);
$$ = $1;
$$ = std::move($1);
} |
attr TOK_UNIQUE {
AstNode *context = extra->ast_stack.back();
@ -2953,25 +2945,25 @@ if_attr:
err_at_loc(@2, "unique keyword cannot be used for 'else if' branch.");
(*$1)[ID::full_case] = AstNode::mkconst_int(@$, 1, false);
(*$1)[ID::parallel_case] = AstNode::mkconst_int(@$, 1, false);
$$ = $1;
$$ = std::move($1);
};
case_attr:
attr {
$$ = $1;
$$ = std::move($1);
} |
attr TOK_UNIQUE0 {
(*$1)[ID::parallel_case] = AstNode::mkconst_int(@$, 1, false);
$$ = $1;
$$ = std::move($1);
} |
attr TOK_PRIORITY {
(*$1)[ID::full_case] = AstNode::mkconst_int(@$, 1, false);
$$ = $1;
$$ = std::move($1);
} |
attr TOK_UNIQUE {
(*$1)[ID::full_case] = AstNode::mkconst_int(@$, 1, false);
(*$1)[ID::parallel_case] = AstNode::mkconst_int(@$, 1, false);
$$ = $1;
$$ = std::move($1);
};
case_type:
@ -3139,9 +3131,7 @@ module_gen_body:
gen_stmt_or_module_body_stmt:
gen_stmt | module_body_stmt |
attr TOK_SEMICOL {
free_attr($1);
};
attr TOK_SEMICOL;
genvar_identifier:
TOK_ID {
@ -3240,10 +3230,10 @@ expr:
$$->children.push_back(std::move($4));
$$->children.push_back(std::move($6));
SET_AST_NODE_LOC($$.get(), @1, @$);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
inc_or_dec_op attr rvalue {
$$ = extra->addIncOrDecExpr(std::move($3), $2, $1, location_range(@1, @3), false, mode->sv);
$$ = extra->addIncOrDecExpr(std::move($3), std::move($2), $1, location_range(@1, @3), false, mode->sv);
} |
// TODO: Attributes are allowed in the middle here, but they create some
// non-trivial conflicts that don't seem worth solving for now.
@ -3257,16 +3247,16 @@ basic_expr:
} |
TOK_LPAREN expr TOK_RPAREN integral_number {
if ($4->compare(0, 1, "'") != 0)
err_at_loc(@4, "Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", $4->c_str());
err_at_loc(@4, "Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", *$4);
ConstParser p{@4};
auto val = p.const2ast(*$4, extra->case_type_stack.size() == 0 ? 0 : extra->case_type_stack.back(), !mode->lib);
if (val == nullptr)
log_error("Value conversion failed: `%s'\n", $4->c_str());
log_error("Value conversion failed: `%s'\n", *$4);
$$ = std::make_unique<AstNode>(@$, AST_TO_BITS, std::move($2), std::move(val));
} |
hierarchical_id integral_number {
if ($2->compare(0, 1, "'") != 0)
err_at_loc(@2, "Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", $2->c_str());
err_at_loc(@2, "Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", *$2);
auto bits = std::make_unique<AstNode>(@$, AST_IDENTIFIER);
bits->str = *$1;
SET_AST_NODE_LOC(bits.get(), @1, @1);
@ -3274,7 +3264,7 @@ basic_expr:
auto val = p.const2ast(*$2, extra->case_type_stack.size() == 0 ? 0 : extra->case_type_stack.back(), !mode->lib);
SET_AST_NODE_LOC(val.get(), @2, @2);
if (val == nullptr)
log_error("Value conversion failed: `%s'\n", $2->c_str());
log_error("Value conversion failed: `%s'\n", *$2);
$$ = std::make_unique<AstNode>(@$, AST_TO_BITS, std::move(bits), std::move(val));
} |
integral_number {
@ -3282,7 +3272,7 @@ basic_expr:
$$ = p.const2ast(*$1, extra->case_type_stack.size() == 0 ? 0 : extra->case_type_stack.back(), !mode->lib);
SET_AST_NODE_LOC($$.get(), @1, @1);
if ($$ == nullptr)
log_error("Value conversion failed: `%s'\n", $1->c_str());
log_error("Value conversion failed: `%s'\n", *$1);
} |
TOK_REALVAL {
$$ = std::make_unique<AstNode>(@$, AST_REALVALUE);
@ -3305,18 +3295,18 @@ basic_expr:
node->str = *$1;
extra->ast_stack.push_back(node);
SET_AST_NODE_LOC(node, @1, @1);
append_attr(node, $2);
append_attr(node, std::move($2));
} TOK_LPAREN arg_list optional_comma TOK_RPAREN {
$$.reset(extra->ast_stack.back());
extra->ast_stack.pop_back();
} |
TOK_TO_SIGNED attr TOK_LPAREN expr TOK_RPAREN {
$$ = std::make_unique<AstNode>(@$, AST_TO_SIGNED, std::move($4));
append_attr($$.get(), $2);
append_attr($$.get(), std::move($2));
} |
TOK_TO_UNSIGNED attr TOK_LPAREN expr TOK_RPAREN {
$$ = std::make_unique<AstNode>(@$, AST_TO_UNSIGNED, std::move($4));
append_attr($$.get(), $2);
append_attr($$.get(), std::move($2));
} |
TOK_LPAREN expr TOK_RPAREN {
$$ = std::move($2);
@ -3333,47 +3323,47 @@ basic_expr:
TOK_TILDE attr basic_expr %prec UNARY_OPS {
$$ = std::make_unique<AstNode>(@$, AST_BIT_NOT, std::move($3));
SET_AST_NODE_LOC($$.get(), @1, @3);
append_attr($$.get(), $2);
append_attr($$.get(), std::move($2));
} |
basic_expr TOK_AMP attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_BIT_AND, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr OP_NAND attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_BIT_NOT, std::make_unique<AstNode>(@$, AST_BIT_AND, std::move($1), std::move($4)));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr TOK_PIPE attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_BIT_OR, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr OP_NOR attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_BIT_NOT, std::make_unique<AstNode>(@$, AST_BIT_OR, std::move($1), std::move($4)));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr TOK_CARET attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_BIT_XOR, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr OP_XNOR attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_BIT_XNOR, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
TOK_AMP attr basic_expr %prec UNARY_OPS {
$$ = std::make_unique<AstNode>(@$, AST_REDUCE_AND, std::move($3));
SET_AST_NODE_LOC($$.get(), @1, @3);
append_attr($$.get(), $2);
append_attr($$.get(), std::move($2));
} |
OP_NAND attr basic_expr %prec UNARY_OPS {
$$ = std::make_unique<AstNode>(@$, AST_REDUCE_AND, std::move($3));
SET_AST_NODE_LOC($$.get(), @1, @3);
append_attr($$.get(), $2);
append_attr($$.get(), std::move($2));
$$ = std::make_unique<AstNode>(@$, AST_LOGIC_NOT, std::move($$));
} |
TOK_PIPE attr basic_expr %prec UNARY_OPS {
@ -3384,134 +3374,134 @@ basic_expr:
OP_NOR attr basic_expr %prec UNARY_OPS {
$$ = std::make_unique<AstNode>(@$, AST_REDUCE_OR, std::move($3));
SET_AST_NODE_LOC($$.get(), @1, @3);
append_attr($$.get(), $2);
append_attr($$.get(), std::move($2));
$$ = std::make_unique<AstNode>(@$, AST_LOGIC_NOT, std::move($$));
SET_AST_NODE_LOC($$.get(), @1, @3);
} |
TOK_CARET attr basic_expr %prec UNARY_OPS {
$$ = std::make_unique<AstNode>(@$, AST_REDUCE_XOR, std::move($3));
SET_AST_NODE_LOC($$.get(), @1, @3);
append_attr($$.get(), $2);
append_attr($$.get(), std::move($2));
} |
OP_XNOR attr basic_expr %prec UNARY_OPS {
$$ = std::make_unique<AstNode>(@$, AST_REDUCE_XNOR, std::move($3));
SET_AST_NODE_LOC($$.get(), @1, @3);
append_attr($$.get(), $2);
append_attr($$.get(), std::move($2));
} |
basic_expr OP_SHL attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_SHIFT_LEFT, std::move($1), std::make_unique<AstNode>(@$, AST_TO_UNSIGNED, std::move($4)));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr OP_SHR attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_SHIFT_RIGHT, std::move($1), std::make_unique<AstNode>(@$, AST_TO_UNSIGNED, std::move($4)));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr OP_SSHL attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_SHIFT_SLEFT, std::move($1), std::make_unique<AstNode>(@$, AST_TO_UNSIGNED, std::move($4)));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr OP_SSHR attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_SHIFT_SRIGHT, std::move($1), std::make_unique<AstNode>(@$, AST_TO_UNSIGNED, std::move($4)));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr TOK_LT attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_LT, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr OP_LE attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_LE, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr OP_EQ attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_EQ, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr OP_NE attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_NE, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr OP_EQX attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_EQX, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr OP_NEX attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_NEX, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr OP_GE attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_GE, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr TOK_GT attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_GT, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr TOK_PLUS attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_ADD, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr TOK_MINUS attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_SUB, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr TOK_ASTER attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_MUL, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr TOK_SLASH attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_DIV, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr TOK_PERC attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_MOD, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr OP_POW attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_POW, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
TOK_PLUS attr basic_expr %prec UNARY_OPS {
$$ = std::make_unique<AstNode>(@$, AST_POS, std::move($3));
SET_AST_NODE_LOC($$.get(), @1, @3);
append_attr($$.get(), $2);
append_attr($$.get(), std::move($2));
} |
TOK_MINUS attr basic_expr %prec UNARY_OPS {
$$ = std::make_unique<AstNode>(@$, AST_NEG, std::move($3));
SET_AST_NODE_LOC($$.get(), @1, @3);
append_attr($$.get(), $2);
append_attr($$.get(), std::move($2));
} |
basic_expr OP_LAND attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_LOGIC_AND, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
basic_expr OP_LOR attr basic_expr {
$$ = std::make_unique<AstNode>(@$, AST_LOGIC_OR, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
append_attr($$.get(), std::move($3));
} |
TOK_EXCL attr basic_expr %prec UNARY_OPS {
$$ = std::make_unique<AstNode>(@$, AST_LOGIC_NOT, std::move($3));
SET_AST_NODE_LOC($$.get(), @1, @3);
append_attr($$.get(), $2);
append_attr($$.get(), std::move($2));
} |
TOK_SIGNED OP_CAST TOK_LPAREN expr TOK_RPAREN {
if (!mode->sv)