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simplify.cc: Fix unsized const in params

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This commit is contained in:
Krystine Sherwin 2025-11-07 15:52:24 +13:00
parent 5d0847f6fb
commit a5cc905184
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2 changed files with 16 additions and 3 deletions
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10
frontends/ast/simplify.cc
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@ -2231,9 +2231,13 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
}
if (children[0]->type == AST_CONSTANT) {
if (width != int(children[0]->bits.size())) {
RTLIL::SigSpec sig(children[0]->bits);
sig.extend_u0(width, children[0]->is_signed);
children[0] = mkconst_bits(location, sig.as_const().to_bits(), is_signed);
RTLIL::Const val;
if (children[0]->is_unsized) {
val = children[0]->bitsAsUnsizedConst(width);
} else {
val = children[0]->bitsAsConst(width);
}
children[0] = mkconst_bits(location, val.to_bits(), is_signed);
fixup_hierarchy_flags();
}
children[0]->is_signed = is_signed;

9
tests/verilog/unbased_unsized.sv
View file

@ -6,6 +6,11 @@ module pass_through(
endmodule
module top;
localparam logic [63:0]
l01 = '0,
l02 = '1,
l03 = 'x,
l04 = 'z;
logic [63:0]
o01, o02, o03, o04,
o05, o06, o07, o08,
@ -36,5 +41,9 @@ module top;
assert (o10 === {64 {1'b1}});
assert (o11 === {64 {1'bx}});
assert (o12 === {64 {1'bz}});
assert (l01 === {64 {1'b0}});
assert (l02 === {64 {1'b1}});
assert (l03 === {64 {1'bx}});
assert (l04 === {64 {1'bz}});
end
endmodule