1857 commits

Author	SHA1	Message	Date
Clifford Wolf	9cf12570ba	Added support for YOSYS_COVER_DIR env variable	2014-07-24 03:49:32 +02:00
Clifford Wolf	6b1018314c	Added cover() API	2014-07-24 03:48:38 +02:00
Clifford Wolf	82fa356037	Added hashing to RTLIL::SigSpec relational and equal operators	2014-07-23 23:58:03 +02:00
Clifford Wolf	f368d792fb	Disabled RTLIL::SigSpec::check() in release builds	2014-07-23 21:42:44 +02:00
Clifford Wolf	95ac484548	Fixed release build	2014-07-23 21:38:18 +02:00
Clifford Wolf	2a41afb7b2	Added RTLIL::SigSpec::repeat()	2014-07-23 21:34:14 +02:00
Clifford Wolf	c094c53de8	Removed RTLIL::SigSpec::optimize()	2014-07-23 20:32:28 +02:00
Clifford Wolf	8fd8e4a468	Turned RTLIL::SigSpec::optimize() to a no-op: a packed SigSpec is now always optimized	2014-07-23 20:11:55 +02:00
Clifford Wolf	a62c21c9c6	Removed RTLIL::SigSpec::expand() method	2014-07-23 19:34:51 +02:00
Clifford Wolf	4e802eb7f6	Fixed all users of SigSpec::chunks_rw() and removed it	2014-07-23 15:36:09 +02:00
Clifford Wolf	85db102e13	Replaced RTLIL::SigSpec::operator!=() with inline version	2014-07-23 15:35:09 +02:00
Clifford Wolf	ec923652e2	Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	2014-07-23 09:52:55 +02:00
Clifford Wolf	a8d3a68971	Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	2014-07-23 09:49:43 +02:00
Clifford Wolf	260c19ec5a	Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3	2014-07-23 09:34:47 +02:00
Clifford Wolf	c61467a32c	Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&)	2014-07-23 08:59:54 +02:00
Clifford Wolf	115dd959d9	SigSpec refactoring: More cleanups of old SigSpec use pattern	2014-07-22 23:50:21 +02:00
Clifford Wolf	9e94f41b89	SigSpec refactoring: Added RTLIL::SigSpecIterator	2014-07-22 23:49:26 +02:00
Clifford Wolf	f80da7b41d	SigSpec refactoring: added RTLIL::SigSpec::operator[]	2014-07-22 22:54:03 +02:00
Clifford Wolf	fd4cbe6275	SigSpec refactoring: rewrote some RTLIL::SigSpec methods to use unpacked form	2014-07-22 22:26:30 +02:00
Clifford Wolf	a97be0828a	Removed RTLIL::SigChunk::compare()	2014-07-22 21:40:52 +02:00
Clifford Wolf	08e1e25169	SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api	2014-07-22 21:33:52 +02:00
Clifford Wolf	28b3fd05fa	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()	2014-07-22 20:58:44 +02:00
Clifford Wolf	7bffde6abd	SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only	2014-07-22 20:39:38 +02:00
Clifford Wolf	4b4048bc5f	SigSpec refactoring: using the accessor functions everywhere	2014-07-22 20:39:37 +02:00
Clifford Wolf	16e5ae0b92	SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and added accessor functions	2014-07-22 20:39:37 +02:00
Clifford Wolf	a233762a81	SigSpec refactoring: renamed chunks and width to __chunks and __width	2014-07-22 20:39:37 +02:00
Clifford Wolf	550ac35873	Added support for scripts with labels	2014-07-21 13:28:18 +02:00
Clifford Wolf	361e0d62ff	Replaced depricated NEW_WIRE macro with module->addWire() calls	2014-07-21 12:42:02 +02:00
Clifford Wolf	1d88f1cf9f	Removed deprecated module->new_wire()	2014-07-21 12:35:06 +02:00
Clifford Wolf	c54d1f2ad1	Bugfix in satgen for cells with wider in- than outputs.	2014-07-21 12:03:41 +02:00
Clifford Wolf	54b0f2e659	Added module->remove(), module->addWire(), module->addCell(), cell->check()	2014-07-21 12:02:55 +02:00
Clifford Wolf	caae6e19df	Added log_ping()	2014-07-21 12:01:45 +02:00
Clifford Wolf	8d04ca7d22	Added call_on_selection() and call_on_module() API	2014-07-20 15:33:06 +02:00
Clifford Wolf	e57db5e9b2	Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion	2014-07-20 11:01:04 +02:00
Clifford Wolf	efa7884026	Added SIZE() macro	2014-07-20 10:36:14 +02:00
Clifford Wolf	a6174aaf5e	Added log_cell()	2014-07-20 10:35:47 +02:00
Clifford Wolf	02f0acb3bc	Fixed log_id() memory corruption	2014-07-19 20:53:29 +02:00
Clifford Wolf	35edac0b31	Added ModWalker helper class	2014-07-19 15:33:00 +02:00
Clifford Wolf	1c288adcc0	Some "const" cleanups in SigMap	2014-07-19 15:32:39 +02:00
Clifford Wolf	a721f7d768	Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>	2014-07-18 11:36:34 +02:00
Clifford Wolf	2d69c309f9	Added function-like cell creation helpers	2014-07-18 10:27:06 +02:00
Clifford Wolf	a8cedb2257	Added log_id() helper function	2014-07-18 10:26:01 +02:00
Clifford Wolf	274c514879	Fixed RTLIL::SigSpec::append_bit() for appending constants	2014-07-17 12:10:57 +02:00
Clifford Wolf	73e0e13d2f	Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal	2014-07-16 11:38:02 +02:00
Clifford Wolf	847e2ee4a1	Use "verilog -sv" to parse .sv files	2014-07-11 13:10:51 +02:00
Clifford Wolf	e275e8eef9	Add support for cell arrays	2014-06-07 11:48:50 +02:00
Clifford Wolf	f9c1cd5edb	Improved error message for options after front-end filename arguments	2014-06-04 09:10:50 +02:00
Clifford Wolf	a5a519a9d1	workaround for OpenBSD 'stdout' implementation	2014-05-03 12:55:56 +02:00
Clifford Wolf	75a5d6bd1e	workaround for OpenBSD 'stdin' implementation	2014-05-02 13:22:26 +02:00
Clifford Wolf	d4a1b0af5b	Added support for dlatchsr cells	2014-03-31 14:14:40 +02:00