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Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal

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Clifford Wolf 2014-07-16 11:38:02 +02:00
parent 964a67ac41
commit 73e0e13d2f
2 changed files with 6 additions and 5 deletions
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4
kernel/rtlil.cc
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@ -619,7 +619,7 @@ namespace {
param_bool("\\CLK_POLARITY");
param("\\PRIORITY");
port("\\CLK", 1);
port("\\EN", 1);
port("\\EN", param("\\WIDTH"));
port("\\ADDR", param("\\ABITS"));
port("\\DATA", param("\\WIDTH"));
check_expected();
@ -639,7 +639,7 @@ namespace {
port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
port("\\WR_CLK", param("\\WR_PORTS"));
port("\\WR_EN", param("\\WR_PORTS"));
port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
check_expected();