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SigSpec refactoring: using the accessor functions everywhere

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This commit is contained in:
Clifford Wolf 2014-07-22 20:15:14 +02:00
parent 16e5ae0b92
commit 4b4048bc5f
62 changed files with 800 additions and 800 deletions
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12
kernel/bitpattern.h
View file

@ -31,16 +31,16 @@ struct BitPatternPool
BitPatternPool(RTLIL::SigSpec sig)
{
width = sig.__width;
width = sig.size();
if (width > 0) {
std::vector<RTLIL::State> pattern(width);
sig.optimize();
for (int i = 0; i < width; i++) {
RTLIL::SigSpec s = sig.extract(i, 1);
s.optimize();
assert(s.__chunks.size() == 1);
if (s.__chunks[0].wire == NULL && s.__chunks[0].data.bits[0] <= RTLIL::State::S1)
pattern[i] = s.__chunks[0].data.bits[0];
assert(s.chunks().size() == 1);
if (s.chunks()[0].wire == NULL && s.chunks()[0].data.bits[0] <= RTLIL::State::S1)
pattern[i] = s.chunks()[0].data.bits[0];
else
pattern[i] = RTLIL::State::Sa;
}
@ -63,8 +63,8 @@ struct BitPatternPool
{
sig.optimize();
assert(sig.is_fully_const());
assert(sig.__chunks.size() == 1);
bits_t bits = sig.__chunks[0].data.bits;
assert(sig.chunks().size() == 1);
bits_t bits = sig.chunks()[0].data.bits;
for (auto &b : bits)
if (b > RTLIL::State::S1)
b = RTLIL::State::Sa;

18
kernel/consteval.h
View file

@ -72,8 +72,8 @@ struct ConstEval
#ifndef NDEBUG
RTLIL::SigSpec current_val = values_map(sig);
current_val.expand();
for (size_t i = 0; i < current_val.__chunks.size(); i++) {
RTLIL::SigChunk &chunk = current_val.__chunks[i];
for (size_t i = 0; i < current_val.chunks().size(); i++) {
RTLIL::SigChunk &chunk = current_val.chunks()[i];
assert(chunk.wire != NULL || chunk.data.bits[0] == value.bits[i]);
}
#endif
@ -113,10 +113,10 @@ struct ConstEval
int count_maybe_set_s_bits = 0;
int count_set_s_bits = 0;
for (int i = 0; i < sig_s.__width; i++)
for (int i = 0; i < sig_s.size(); i++)
{
RTLIL::State s_bit = sig_s.extract(i, 1).as_const().bits.at(0);
RTLIL::SigSpec b_slice = sig_b.extract(sig_y.__width*i, sig_y.__width);
RTLIL::SigSpec b_slice = sig_b.extract(sig_y.size()*i, sig_y.size());
if (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1)
y_candidates.push_back(b_slice);
@ -162,9 +162,9 @@ struct ConstEval
}
else
{
if (sig_a.__width > 0 && !eval(sig_a, undef, cell))
if (sig_a.size() > 0 && !eval(sig_a, undef, cell))
return false;
if (sig_b.__width > 0 && !eval(sig_b, undef, cell))
if (sig_b.size() > 0 && !eval(sig_b, undef, cell))
return false;
set(sig_y, CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const()));
}
@ -210,9 +210,9 @@ struct ConstEval
if (sig.is_fully_const())
return true;
for (size_t i = 0; i < sig.__chunks.size(); i++)
if (sig.__chunks[i].wire != NULL)
undef.append(sig.__chunks[i]);
for (size_t i = 0; i < sig.chunks().size(); i++)
if (sig.chunks()[i].wire != NULL)
undef.append(sig.chunks()[i]);
return false;
}

88
kernel/rtlil.cc
View file

@ -350,7 +350,7 @@ namespace {
{
if (cell->connections.count(name) == 0)
error(__LINE__);
if (cell->connections.at(name).__width != width)
if (cell->connections.at(name).size() != width)
error(__LINE__);
expected_ports.insert(name);
}
@ -381,7 +381,7 @@ namespace {
char portname[3] = { '\\', *p, 0 };
if (cell->connections.count(portname) == 0)
error(__LINE__);
if (cell->connections.at(portname).__width != 1)
if (cell->connections.at(portname).size() != 1)
error(__LINE__);
}
@ -755,7 +755,7 @@ void RTLIL::Module::check()
}
for (auto &it : connections) {
assert(it.first.__width == it.second.__width);
assert(it.first.size() == it.second.size());
it.first.check();
it.second.check();
}
@ -801,7 +801,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
RTLIL::Module *mod;
void operator()(RTLIL::SigSpec &sig)
{
for (auto &c : sig.__chunks)
for (auto &c : sig.chunks())
if (c.wire != NULL)
c.wire = mod->wires.at(c.wire->name);
}
@ -891,8 +891,8 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
cell->name = name; \
cell->type = _type; \
cell->parameters["\\A_SIGNED"] = is_signed; \
cell->parameters["\\A_WIDTH"] = sig_a.__width; \
cell->parameters["\\Y_WIDTH"] = sig_y.__width; \
cell->parameters["\\A_WIDTH"] = sig_a.size(); \
cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
cell->connections["\\A"] = sig_a; \
cell->connections["\\Y"] = sig_y; \
add(cell); \
@ -903,10 +903,10 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
add ## _func(name, sig_a, sig_y, is_signed); \
return sig_y; \
}
DEF_METHOD(Not, sig_a.__width, "$not")
DEF_METHOD(Pos, sig_a.__width, "$pos")
DEF_METHOD(Bu0, sig_a.__width, "$bu0")
DEF_METHOD(Neg, sig_a.__width, "$neg")
DEF_METHOD(Not, sig_a.size(), "$not")
DEF_METHOD(Pos, sig_a.size(), "$pos")
DEF_METHOD(Bu0, sig_a.size(), "$bu0")
DEF_METHOD(Neg, sig_a.size(), "$neg")
DEF_METHOD(ReduceAnd, 1, "$reduce_and")
DEF_METHOD(ReduceOr, 1, "$reduce_or")
DEF_METHOD(ReduceXor, 1, "$reduce_xor")
@ -922,9 +922,9 @@ DEF_METHOD(LogicNot, 1, "$logic_not")
cell->type = _type; \
cell->parameters["\\A_SIGNED"] = is_signed; \
cell->parameters["\\B_SIGNED"] = is_signed; \
cell->parameters["\\A_WIDTH"] = sig_a.__width; \
cell->parameters["\\B_WIDTH"] = sig_b.__width; \
cell->parameters["\\Y_WIDTH"] = sig_y.__width; \
cell->parameters["\\A_WIDTH"] = sig_a.size(); \
cell->parameters["\\B_WIDTH"] = sig_b.size(); \
cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
cell->connections["\\A"] = sig_a; \
cell->connections["\\B"] = sig_b; \
cell->connections["\\Y"] = sig_y; \
@ -936,14 +936,14 @@ DEF_METHOD(LogicNot, 1, "$logic_not")
add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
return sig_y; \
}
DEF_METHOD(And, std::max(sig_a.__width, sig_b.__width), "$and")
DEF_METHOD(Or, std::max(sig_a.__width, sig_b.__width), "$or")
DEF_METHOD(Xor, std::max(sig_a.__width, sig_b.__width), "$xor")
DEF_METHOD(Xnor, std::max(sig_a.__width, sig_b.__width), "$xnor")
DEF_METHOD(Shl, sig_a.__width, "$shl")
DEF_METHOD(Shr, sig_a.__width, "$shr")
DEF_METHOD(Sshl, sig_a.__width, "$sshl")
DEF_METHOD(Sshr, sig_a.__width, "$sshr")
DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and")
DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or")
DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor")
DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor")
DEF_METHOD(Shl, sig_a.size(), "$shl")
DEF_METHOD(Shr, sig_a.size(), "$shr")
DEF_METHOD(Sshl, sig_a.size(), "$sshl")
DEF_METHOD(Sshr, sig_a.size(), "$sshr")
DEF_METHOD(Lt, 1, "$lt")
DEF_METHOD(Le, 1, "$le")
DEF_METHOD(Eq, 1, "$eq")
@ -952,11 +952,11 @@ DEF_METHOD(Eqx, 1, "$eqx")
DEF_METHOD(Nex, 1, "$nex")
DEF_METHOD(Ge, 1, "$ge")
DEF_METHOD(Gt, 1, "$gt")
DEF_METHOD(Add, std::max(sig_a.__width, sig_b.__width), "$add")
DEF_METHOD(Sub, std::max(sig_a.__width, sig_b.__width), "$sub")
DEF_METHOD(Mul, std::max(sig_a.__width, sig_b.__width), "$mul")
DEF_METHOD(Div, std::max(sig_a.__width, sig_b.__width), "$div")
DEF_METHOD(Mod, std::max(sig_a.__width, sig_b.__width), "$mod")
DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add")
DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub")
DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul")
DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div")
DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod")
DEF_METHOD(LogicAnd, 1, "$logic_and")
DEF_METHOD(LogicOr, 1, "$logic_or")
#undef DEF_METHOD
@ -966,9 +966,9 @@ DEF_METHOD(LogicOr, 1, "$logic_or")
RTLIL::Cell *cell = new RTLIL::Cell; \
cell->name = name; \
cell->type = _type; \
cell->parameters["\\WIDTH"] = sig_a.__width; \
cell->parameters["\\WIDTH"] = sig_b.__width; \
if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.__width; \
cell->parameters["\\WIDTH"] = sig_a.size(); \
cell->parameters["\\WIDTH"] = sig_b.size(); \
if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
cell->connections["\\A"] = sig_a; \
cell->connections["\\B"] = sig_b; \
cell->connections["\\S"] = sig_s; \
@ -977,7 +977,7 @@ DEF_METHOD(LogicOr, 1, "$logic_or")
return cell; \
} \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.__width); \
RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
return sig_y; \
}
@ -1050,9 +1050,9 @@ RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, R
cell->type = "$pow";
cell->parameters["\\A_SIGNED"] = a_signed;
cell->parameters["\\B_SIGNED"] = b_signed;
cell->parameters["\\A_WIDTH"] = sig_a.__width;
cell->parameters["\\B_WIDTH"] = sig_b.__width;
cell->parameters["\\Y_WIDTH"] = sig_y.__width;
cell->parameters["\\A_WIDTH"] = sig_a.size();
cell->parameters["\\B_WIDTH"] = sig_b.size();
cell->parameters["\\Y_WIDTH"] = sig_y.size();
cell->connections["\\A"] = sig_a;
cell->connections["\\B"] = sig_b;
cell->connections["\\Y"] = sig_y;
@ -1065,8 +1065,8 @@ RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a,
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = name;
cell->type = "$slice";
cell->parameters["\\A_WIDTH"] = sig_a.__width;
cell->parameters["\\Y_WIDTH"] = sig_y.__width;
cell->parameters["\\A_WIDTH"] = sig_a.size();
cell->parameters["\\Y_WIDTH"] = sig_y.size();
cell->parameters["\\OFFSET"] = offset;
cell->connections["\\A"] = sig_a;
cell->connections["\\Y"] = sig_y;
@ -1079,8 +1079,8 @@ RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = name;
cell->type = "$concat";
cell->parameters["\\A_WIDTH"] = sig_a.__width;
cell->parameters["\\B_WIDTH"] = sig_b.__width;
cell->parameters["\\A_WIDTH"] = sig_a.size();
cell->parameters["\\B_WIDTH"] = sig_b.size();
cell->connections["\\A"] = sig_a;
cell->connections["\\B"] = sig_b;
cell->connections["\\Y"] = sig_y;
@ -1094,7 +1094,7 @@ RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, R
cell->name = name;
cell->type = "$lut";
cell->parameters["\\LUT"] = lut;
cell->parameters["\\WIDTH"] = sig_i.__width;
cell->parameters["\\WIDTH"] = sig_i.size();
cell->connections["\\I"] = sig_i;
cell->connections["\\O"] = sig_o;
add(cell);
@ -1119,7 +1119,7 @@ RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set,
cell->type = "$sr";
cell->parameters["\\SET_POLARITY"] = set_polarity;
cell->parameters["\\CLR_POLARITY"] = clr_polarity;
cell->parameters["\\WIDTH"] = sig_q.__width;
cell->parameters["\\WIDTH"] = sig_q.size();
cell->connections["\\SET"] = sig_set;
cell->connections["\\CLR"] = sig_clr;
cell->connections["\\Q"] = sig_q;
@ -1133,7 +1133,7 @@ RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk,
cell->name = name;
cell->type = "$dff";
cell->parameters["\\CLK_POLARITY"] = clk_polarity;
cell->parameters["\\WIDTH"] = sig_q.__width;
cell->parameters["\\WIDTH"] = sig_q.size();
cell->connections["\\CLK"] = sig_clk;
cell->connections["\\D"] = sig_d;
cell->connections["\\Q"] = sig_q;
@ -1150,7 +1150,7 @@ RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_cl
cell->parameters["\\CLK_POLARITY"] = clk_polarity;
cell->parameters["\\SET_POLARITY"] = set_polarity;
cell->parameters["\\CLR_POLARITY"] = clr_polarity;
cell->parameters["\\WIDTH"] = sig_q.__width;
cell->parameters["\\WIDTH"] = sig_q.size();
cell->connections["\\CLK"] = sig_clk;
cell->connections["\\SET"] = sig_set;
cell->connections["\\CLR"] = sig_clr;
@ -1169,7 +1169,7 @@ RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk
cell->parameters["\\CLK_POLARITY"] = clk_polarity;
cell->parameters["\\ARST_POLARITY"] = arst_polarity;
cell->parameters["\\ARST_VALUE"] = arst_value;
cell->parameters["\\WIDTH"] = sig_q.__width;
cell->parameters["\\WIDTH"] = sig_q.size();
cell->connections["\\CLK"] = sig_clk;
cell->connections["\\ARST"] = sig_arst;
cell->connections["\\D"] = sig_d;
@ -1184,7 +1184,7 @@ RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_e
cell->name = name;
cell->type = "$dlatch";
cell->parameters["\\EN_POLARITY"] = en_polarity;
cell->parameters["\\WIDTH"] = sig_q.__width;
cell->parameters["\\WIDTH"] = sig_q.size();
cell->connections["\\EN"] = sig_en;
cell->connections["\\D"] = sig_d;
cell->connections["\\Q"] = sig_q;
@ -1201,7 +1201,7 @@ RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig
cell->parameters["\\EN_POLARITY"] = en_polarity;
cell->parameters["\\SET_POLARITY"] = set_polarity;
cell->parameters["\\CLR_POLARITY"] = clr_polarity;
cell->parameters["\\WIDTH"] = sig_q.__width;
cell->parameters["\\WIDTH"] = sig_q.size();
cell->connections["\\EN"] = sig_en;
cell->connections["\\SET"] = sig_set;
cell->connections["\\CLR"] = sig_clr;

4
kernel/rtlil.h
View file

@ -560,8 +560,8 @@ public:
};
inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {
assert(sig.__width == 1 && sig.__chunks.size() == 1);
*this = SigBit(sig.__chunks[0]);
assert(sig.size() == 1 && sig.chunks().size() == 1);
*this = SigBit(sig.chunks()[0]);
}
struct RTLIL::CaseRule {

14
kernel/satgen.h
View file

@ -55,9 +55,9 @@ struct SatGen
sig.expand();
std::vector<int> vec;
vec.reserve(sig.__chunks.size());
vec.reserve(sig.chunks().size());
for (auto &c : sig.__chunks)
for (auto &c : sig.chunks())
if (c.wire == NULL) {
RTLIL::State bit = c.data.bits.at(0);
if (model_undef && dup_undef && bit == RTLIL::State::Sx)
@ -118,7 +118,7 @@ struct SatGen
if (timestep_rhs < 0)
timestep_rhs = timestep_lhs;
assert(lhs.__width == rhs.__width);
assert(lhs.size() == rhs.size());
std::vector<int> vec_lhs = importSigSpec(lhs, timestep_lhs);
std::vector<int> vec_rhs = importSigSpec(rhs, timestep_rhs);
@ -130,7 +130,7 @@ struct SatGen
std::vector<int> undef_rhs = importUndefSigSpec(rhs, timestep_rhs);
std::vector<int> eq_bits;
for (int i = 0; i < lhs.__width; i++)
for (int i = 0; i < lhs.size(); i++)
eq_bits.push_back(ez->AND(ez->IFF(undef_lhs.at(i), undef_rhs.at(i)),
ez->IFF(ez->OR(vec_lhs.at(i), undef_lhs.at(i)), ez->OR(vec_rhs.at(i), undef_rhs.at(i)))));
return ez->expression(ezSAT::OpAnd, eq_bits);
@ -742,11 +742,11 @@ struct SatGen
only_first_one.at(0) = ez->TRUE;
div_zero_result = ez->vec_ite(a.back(), only_first_one, all_ones);
} else {
div_zero_result.insert(div_zero_result.end(), cell->connections.at("\\A").__width, ez->TRUE);
div_zero_result.insert(div_zero_result.end(), cell->connections.at("\\A").size(), ez->TRUE);
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->FALSE);
}
} else {
int copy_a_bits = std::min(cell->connections.at("\\A").__width, cell->connections.at("\\B").__width);
int copy_a_bits = std::min(cell->connections.at("\\A").size(), cell->connections.at("\\B").size());
div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits);
if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool())
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back());
@ -768,7 +768,7 @@ struct SatGen
{
RTLIL::SigSpec a = cell->connections.at("\\A");
RTLIL::SigSpec y = cell->connections.at("\\Y");
ez->assume(signals_eq(a.extract(cell->parameters.at("\\OFFSET").as_int(), y.__width), y, timestep));
ez->assume(signals_eq(a.extract(cell->parameters.at("\\OFFSET").as_int(), y.size()), y, timestep));
return true;
}

50
kernel/sigtools.h
View file

@ -38,7 +38,7 @@ struct SigPool
void add(RTLIL::SigSpec sig)
{
sig.expand();
for (auto &c : sig.__chunks) {
for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
assert(c.width == 1);
@ -56,7 +56,7 @@ struct SigPool
void del(RTLIL::SigSpec sig)
{
sig.expand();
for (auto &c : sig.__chunks) {
for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
assert(c.width == 1);
@ -75,10 +75,10 @@ struct SigPool
{
from.expand();
to.expand();
assert(from.__chunks.size() == to.__chunks.size());
for (size_t i = 0; i < from.__chunks.size(); i++) {
bitDef_t bit_from(from.__chunks[i].wire, from.__chunks[i].offset);
bitDef_t bit_to(to.__chunks[i].wire, to.__chunks[i].offset);
assert(from.chunks().size() == to.chunks().size());
for (size_t i = 0; i < from.chunks().size(); i++) {
bitDef_t bit_from(from.chunks()[i].wire, from.chunks()[i].offset);
bitDef_t bit_to(to.chunks()[i].wire, to.chunks()[i].offset);
if (bit_from.first == NULL || bit_to.first == NULL)
continue;
if (bits.count(bit_from) > 0)
@ -90,7 +90,7 @@ struct SigPool
{
RTLIL::SigSpec result;
sig.expand();
for (auto &c : sig.__chunks) {
for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
bitDef_t bit(c.wire, c.offset);
@ -104,7 +104,7 @@ struct SigPool
{
RTLIL::SigSpec result;
sig.expand();
for (auto &c : sig.__chunks) {
for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
bitDef_t bit(c.wire, c.offset);
@ -117,7 +117,7 @@ struct SigPool
bool check_any(RTLIL::SigSpec sig)
{
sig.expand();
for (auto &c : sig.__chunks) {
for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
bitDef_t bit(c.wire, c.offset);
@ -130,7 +130,7 @@ struct SigPool
bool check_all(RTLIL::SigSpec sig)
{
sig.expand();
for (auto &c : sig.__chunks) {
for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
bitDef_t bit(c.wire, c.offset);
@ -179,7 +179,7 @@ struct SigSet
void insert(RTLIL::SigSpec sig, T data)
{
sig.expand();
for (auto &c : sig.__chunks) {
for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
assert(c.width == 1);
@ -191,7 +191,7 @@ struct SigSet
void insert(RTLIL::SigSpec sig, const std::set<T> &data)
{
sig.expand();
for (auto &c : sig.__chunks) {
for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
assert(c.width == 1);
@ -203,7 +203,7 @@ struct SigSet
void erase(RTLIL::SigSpec sig)
{
sig.expand();
for (auto &c : sig.__chunks) {
for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
assert(c.width == 1);
@ -215,7 +215,7 @@ struct SigSet
void erase(RTLIL::SigSpec sig, T data)
{
sig.expand();
for (auto &c : sig.__chunks) {
for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
assert(c.width == 1);
@ -227,7 +227,7 @@ struct SigSet
void erase(RTLIL::SigSpec sig, const std::set<T> &data)
{
sig.expand();
for (auto &c : sig.__chunks) {
for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
assert(c.width == 1);
@ -239,7 +239,7 @@ struct SigSet
void find(RTLIL::SigSpec sig, std::set<T> &result)
{
sig.expand();
for (auto &c : sig.__chunks) {
for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
assert(c.width == 1);
@ -259,7 +259,7 @@ struct SigSet
bool has(RTLIL::SigSpec sig)
{
sig.expand();
for (auto &c : sig.__chunks) {
for (auto &c : sig.chunks()) {
if (c.wire == NULL)
continue;
assert(c.width == 1);
@ -420,11 +420,11 @@ struct SigMap
from.expand();
to.expand();
assert(from.__chunks.size() == to.__chunks.size());
for (size_t i = 0; i < from.__chunks.size(); i++)
assert(from.chunks().size() == to.chunks().size());
for (size_t i = 0; i < from.chunks().size(); i++)
{
RTLIL::SigChunk &cf = from.__chunks[i];
RTLIL::SigChunk &ct = to.__chunks[i];
RTLIL::SigChunk &cf = from.chunks()[i];
RTLIL::SigChunk &ct = to.chunks()[i];
if (cf.wire == NULL)
continue;
@ -442,9 +442,9 @@ struct SigMap
void add(RTLIL::SigSpec sig)
{
sig.expand();
for (size_t i = 0; i < sig.__chunks.size(); i++)
for (size_t i = 0; i < sig.chunks().size(); i++)
{
RTLIL::SigChunk &c = sig.__chunks[i];
RTLIL::SigChunk &c = sig.chunks()[i];
if (c.wire != NULL) {
register_bit(c);
set_bit(c, c);
@ -455,14 +455,14 @@ struct SigMap
void del(RTLIL::SigSpec sig)
{
sig.expand();
for (auto &c : sig.__chunks)
for (auto &c : sig.chunks())
unregister_bit(c);
}
void apply(RTLIL::SigSpec &sig) const
{
sig.expand();
for (auto &c : sig.__chunks)
for (auto &c : sig.chunks())
map_bit(c);
sig.optimize();
}