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SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
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parent
7bffde6abd
commit
28b3fd05fa
20 changed files with 29 additions and 34 deletions
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@ -73,7 +73,7 @@ struct ConstEval
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RTLIL::SigSpec current_val = values_map(sig);
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current_val.expand();
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for (size_t i = 0; i < current_val.chunks().size(); i++) {
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RTLIL::SigChunk &chunk = current_val.chunks()[i];
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const RTLIL::SigChunk &chunk = current_val.chunks()[i];
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assert(chunk.wire != NULL || chunk.data.bits[0] == value.bits[i]);
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}
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#endif
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@ -801,7 +801,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
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RTLIL::Module *mod;
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void operator()(RTLIL::SigSpec &sig)
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{
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for (auto &c : sig.chunks())
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for (auto &c : sig.chunks_rw())
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if (c.wire != NULL)
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c.wire = mod->wires.at(c.wire->name);
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}
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@ -501,7 +501,7 @@ private:
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int width_;
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public:
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std::vector<RTLIL::SigChunk> &chunks() { return chunks_; }
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std::vector<RTLIL::SigChunk> &chunks_rw() { return chunks_; }
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const std::vector<RTLIL::SigChunk> &chunks() const { return chunks_; }
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int size() const { return width_; }
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@ -423,8 +423,8 @@ struct SigMap
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assert(from.chunks().size() == to.chunks().size());
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for (size_t i = 0; i < from.chunks().size(); i++)
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{
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RTLIL::SigChunk &cf = from.chunks()[i];
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RTLIL::SigChunk &ct = to.chunks()[i];
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const RTLIL::SigChunk &cf = from.chunks()[i];
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const RTLIL::SigChunk &ct = to.chunks()[i];
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if (cf.wire == NULL)
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continue;
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@ -444,7 +444,7 @@ struct SigMap
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sig.expand();
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for (size_t i = 0; i < sig.chunks().size(); i++)
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{
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RTLIL::SigChunk &c = sig.chunks()[i];
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const RTLIL::SigChunk &c = sig.chunks()[i];
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if (c.wire != NULL) {
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register_bit(c);
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set_bit(c, c);
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@ -462,7 +462,7 @@ struct SigMap
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void apply(RTLIL::SigSpec &sig) const
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{
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sig.expand();
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for (auto &c : sig.chunks())
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for (auto &c : sig.chunks_rw())
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map_bit(c);
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sig.optimize();
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}
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