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SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()

This commit is contained in:
Clifford Wolf 2014-07-22 20:58:44 +02:00
parent 7bffde6abd
commit 28b3fd05fa
20 changed files with 29 additions and 34 deletions

View file

@ -73,7 +73,7 @@ struct ConstEval
RTLIL::SigSpec current_val = values_map(sig);
current_val.expand();
for (size_t i = 0; i < current_val.chunks().size(); i++) {
RTLIL::SigChunk &chunk = current_val.chunks()[i];
const RTLIL::SigChunk &chunk = current_val.chunks()[i];
assert(chunk.wire != NULL || chunk.data.bits[0] == value.bits[i]);
}
#endif

View file

@ -801,7 +801,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
RTLIL::Module *mod;
void operator()(RTLIL::SigSpec &sig)
{
for (auto &c : sig.chunks())
for (auto &c : sig.chunks_rw())
if (c.wire != NULL)
c.wire = mod->wires.at(c.wire->name);
}

View file

@ -501,7 +501,7 @@ private:
int width_;
public:
std::vector<RTLIL::SigChunk> &chunks() { return chunks_; }
std::vector<RTLIL::SigChunk> &chunks_rw() { return chunks_; }
const std::vector<RTLIL::SigChunk> &chunks() const { return chunks_; }
int size() const { return width_; }

View file

@ -423,8 +423,8 @@ struct SigMap
assert(from.chunks().size() == to.chunks().size());
for (size_t i = 0; i < from.chunks().size(); i++)
{
RTLIL::SigChunk &cf = from.chunks()[i];
RTLIL::SigChunk &ct = to.chunks()[i];
const RTLIL::SigChunk &cf = from.chunks()[i];
const RTLIL::SigChunk &ct = to.chunks()[i];
if (cf.wire == NULL)
continue;
@ -444,7 +444,7 @@ struct SigMap
sig.expand();
for (size_t i = 0; i < sig.chunks().size(); i++)
{
RTLIL::SigChunk &c = sig.chunks()[i];
const RTLIL::SigChunk &c = sig.chunks()[i];
if (c.wire != NULL) {
register_bit(c);
set_bit(c, c);
@ -462,7 +462,7 @@ struct SigMap
void apply(RTLIL::SigSpec &sig) const
{
sig.expand();
for (auto &c : sig.chunks())
for (auto &c : sig.chunks_rw())
map_bit(c);
sig.optimize();
}