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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3

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This commit is contained in:
Clifford Wolf 2014-07-23 09:48:26 +02:00
parent a8d3a68971
commit ec923652e2
16 changed files with 43 additions and 51 deletions
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24
kernel/rtlil.cc
View file

@ -1331,13 +1331,11 @@ RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
this->offset = 0;
}
RTLIL::SigChunk RTLIL::SigChunk::grml(RTLIL::Wire *wire, int offset, int width)
RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
{
RTLIL::SigChunk chunk;
chunk.wire = wire;
chunk.width = width;
chunk.offset = offset;
return chunk;
this->wire = wire;
this->width = width;
this->offset = offset;
}
RTLIL::SigChunk::SigChunk(const std::string &str)
@ -1448,13 +1446,11 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
check();
}
RTLIL::SigSpec RTLIL::SigSpec::grml(RTLIL::Wire *wire, int offset, int width)
RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
{
RTLIL::SigSpec sig;
sig.chunks_.push_back(RTLIL::SigChunk::grml(wire, offset, width));
sig.width_ = sig.chunks_.back().width;
sig.check();
return sig;
chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
width_ = chunks_.back().width;
check();
}
RTLIL::SigSpec::SigSpec(const std::string &str)
@ -2152,7 +2148,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
std::vector<std::string> index_tokens;
sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
if (index_tokens.size() == 1)
sig.append(RTLIL::SigSpec::grml(wire, atoi(index_tokens.at(0).c_str())));
sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str())));
else {
int a = atoi(index_tokens.at(0).c_str());
int b = atoi(index_tokens.at(1).c_str());
@ -2160,7 +2156,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
int tmp = a;
a = b, b = tmp;
}
sig.append(RTLIL::SigSpec::grml(wire, a, b-a+1));
sig.append(RTLIL::SigSpec(wire, a, b-a+1));
}
} else
sig.append(wire);

8
kernel/rtlil.h
View file

@ -463,9 +463,7 @@ struct RTLIL::SigChunk {
SigChunk();
SigChunk(const RTLIL::Const &value);
SigChunk(RTLIL::Wire *wire);
SigChunk(RTLIL::Wire *wire, int width); // <-- using this will cause a linker error
SigChunk(RTLIL::Wire *wire, int width, int offset) __attribute__((deprecated));
static SigChunk grml(RTLIL::Wire *wire, int offset, int width = 1);
SigChunk(RTLIL::Wire *wire, int offset, int width = 1);
SigChunk(const std::string &str);
SigChunk(int val, int width = 32);
SigChunk(RTLIL::State bit, int width = 1);
@ -526,9 +524,7 @@ public:
SigSpec(const RTLIL::Const &value);
SigSpec(const RTLIL::SigChunk &chunk);
SigSpec(RTLIL::Wire *wire);
SigSpec(RTLIL::Wire *wire, int width); // <-- using this will cause a linker error
SigSpec(RTLIL::Wire *wire, int width, int offset) __attribute__((deprecated));
static SigSpec grml(RTLIL::Wire *wire, int offset, int width = 1);
SigSpec(RTLIL::Wire *wire, int offset, int width = 1);
SigSpec(const std::string &str);
SigSpec(int val, int width = 32);
SigSpec(RTLIL::State bit, int width = 1);

4
kernel/sigtools.h
View file

@ -144,7 +144,7 @@ struct SigPool
{
RTLIL::SigSpec sig;
for (auto &bit : bits) {
sig.append(RTLIL::SigSpec::grml(bit.first, bit.second));
sig.append(RTLIL::SigSpec(bit.first, bit.second));
break;
}
return sig;
@ -154,7 +154,7 @@ struct SigPool
{
RTLIL::SigSpec sig;
for (auto &bit : bits)
sig.append(RTLIL::SigSpec::grml(bit.first, bit.second));
sig.append(RTLIL::SigSpec(bit.first, bit.second));
sig.sort_and_unify();
return sig;
}