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Removed RTLIL::SigSpec::optimize()

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This commit is contained in:
Clifford Wolf 2014-07-23 20:32:28 +02:00
parent 8fd8e4a468
commit c094c53de8
24 changed files with 15 additions and 181 deletions
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3
kernel/bitpattern.h
View file

@ -34,10 +34,8 @@ struct BitPatternPool
width = sig.size();
if (width > 0) {
std::vector<RTLIL::State> pattern(width);
sig.optimize();
for (int i = 0; i < width; i++) {
RTLIL::SigSpec s = sig.extract(i, 1);
s.optimize();
assert(s.chunks().size() == 1);
if (s.chunks()[0].wire == NULL && s.chunks()[0].data.bits[0] <= RTLIL::State::S1)
pattern[i] = s.chunks()[0].data.bits[0];
@ -61,7 +59,6 @@ struct BitPatternPool
bits_t sig2bits(RTLIL::SigSpec sig)
{
sig.optimize();
assert(sig.is_fully_const());
assert(sig.chunks().size() == 1);
bits_t bits = sig.chunks()[0].data.bits;

114
kernel/rtlil.cc
View file

@ -768,14 +768,6 @@ void RTLIL::Module::check()
void RTLIL::Module::optimize()
{
for (auto &it : cells)
it.second->optimize();
for (auto &it : processes)
it.second->optimize();
for (auto &it : connections) {
it.first.optimize();
it.second.optimize();
}
}
void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
@ -1297,12 +1289,6 @@ RTLIL::Memory::Memory()
size = 0;
}
void RTLIL::Cell::optimize()
{
for (auto &it : connections)
it.second.optimize();
}
void RTLIL::Cell::check()
{
InternalCellChecker checker(NULL, this);
@ -1548,40 +1534,6 @@ bool RTLIL::SigSpec::packed() const
return bits_.empty();
}
void RTLIL::SigSpec::optimize()
{
#if 0
pack();
std::vector<RTLIL::SigChunk> new_chunks;
for (auto &c : chunks_)
if (new_chunks.size() == 0) {
new_chunks.push_back(c);
} else {
RTLIL::SigChunk &cc = new_chunks.back();
if (c.wire == NULL && cc.wire == NULL)
cc.data.bits.insert(cc.data.bits.end(), c.data.bits.begin(), c.data.bits.end());
if (c.wire == cc.wire && (c.wire == NULL || cc.offset + cc.width == c.offset))
cc.width += c.width;
else
new_chunks.push_back(c);
}
chunks_.swap(new_chunks);
check();
#endif
}
RTLIL::SigSpec RTLIL::SigSpec::optimized() const
{
#if 0
pack();
RTLIL::SigSpec ret = *this;
ret.optimize();
return ret;
#else
return *this;
#endif
}
void RTLIL::SigSpec::sort()
{
unpack();
@ -1825,8 +1777,6 @@ void RTLIL::SigSpec::extend(int width, bool is_signed)
while (width_ < width)
append(padding);
}
optimize();
}
void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
@ -1844,7 +1794,6 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
append(padding);
}
optimize();
}
void RTLIL::SigSpec::check() const
@ -1888,8 +1837,6 @@ bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
return width_ < other.width_;
RTLIL::SigSpec a = *this, b = other;
a.optimize();
b.optimize();
if (a.chunks_.size() != b.chunks_.size())
return a.chunks_.size() < b.chunks_.size();
@ -1910,8 +1857,6 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
return false;
RTLIL::SigSpec a = *this, b = other;
a.optimize();
b.optimize();
if (a.chunks_.size() != b.chunks_.size())
return false;
@ -1973,22 +1918,18 @@ bool RTLIL::SigSpec::has_marked_bits() const
bool RTLIL::SigSpec::as_bool() const
{
pack();
assert(is_fully_const());
SigSpec sig = *this;
sig.optimize();
if (sig.width_)
return sig.chunks_[0].data.as_bool();
assert(is_fully_const() && SIZE(chunks_) <= 1);
if (width_)
return chunks_[0].data.as_bool();
return false;
}
int RTLIL::SigSpec::as_int() const
{
pack();
assert(is_fully_const());
SigSpec sig = *this;
sig.optimize();
if (sig.width_)
return sig.chunks_[0].data.as_int();
assert(is_fully_const() && SIZE(chunks_) <= 1);
if (width_)
return chunks_[0].data.as_int();
return 0;
}
@ -2010,11 +1951,9 @@ std::string RTLIL::SigSpec::as_string() const
RTLIL::Const RTLIL::SigSpec::as_const() const
{
pack();
assert(is_fully_const());
SigSpec sig = *this;
sig.optimize();
if (sig.width_)
return sig.chunks_[0].data;
assert(is_fully_const() && SIZE(chunks_) <= 1);
if (width_)
return chunks_[0].data;
return RTLIL::Const();
}
@ -2200,18 +2139,6 @@ RTLIL::CaseRule::~CaseRule()
delete *it;
}
void RTLIL::CaseRule::optimize()
{
for (auto it : switches)
it->optimize();
for (auto &it : compare)
it.optimize();
for (auto &it : actions) {
it.first.optimize();
it.second.optimize();
}
}
RTLIL::CaseRule *RTLIL::CaseRule::clone() const
{
RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
@ -2228,13 +2155,6 @@ RTLIL::SwitchRule::~SwitchRule()
delete *it;
}
void RTLIL::SwitchRule::optimize()
{
signal.optimize();
for (auto it : cases)
it->optimize();
}
RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
{
RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
@ -2246,15 +2166,6 @@ RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
}
void RTLIL::SyncRule::optimize()
{
signal.optimize();
for (auto &it : actions) {
it.first.optimize();
it.second.optimize();
}
}
RTLIL::SyncRule *RTLIL::SyncRule::clone() const
{
RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
@ -2270,13 +2181,6 @@ RTLIL::Process::~Process()
delete *it;
}
void RTLIL::Process::optimize()
{
root_case.optimize();
for (auto it : syncs)
it->optimize();
}
RTLIL::Process *RTLIL::Process::clone() const
{
RTLIL::Process *new_proc = new RTLIL::Process;

7
kernel/rtlil.h
View file

@ -450,7 +450,6 @@ struct RTLIL::Cell {
std::map<RTLIL::IdString, RTLIL::SigSpec> connections;
std::map<RTLIL::IdString, RTLIL::Const> parameters;
RTLIL_ATTRIBUTE_MEMBERS
void optimize();
void check();
template<typename T> void rewrite_sigspecs(T functor);
@ -544,9 +543,6 @@ public:
inline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }
inline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; }
void optimize();
RTLIL::SigSpec optimized() const;
void sort();
void sort_and_unify();
@ -624,7 +620,6 @@ struct RTLIL::SwitchRule {
RTLIL_ATTRIBUTE_MEMBERS
std::vector<RTLIL::CaseRule*> cases;
~SwitchRule();
void optimize();
template<typename T> void rewrite_sigspecs(T functor);
RTLIL::SwitchRule *clone() const;
@ -634,7 +629,6 @@ struct RTLIL::SyncRule {
RTLIL::SyncType type;
RTLIL::SigSpec signal;
std::vector<RTLIL::SigSig> actions;
void optimize();
template<typename T> void rewrite_sigspecs(T functor);
RTLIL::SyncRule *clone() const;
@ -646,7 +640,6 @@ struct RTLIL::Process {
RTLIL::CaseRule root_case;
std::vector<RTLIL::SyncRule*> syncs;
~Process();
void optimize();
template<typename T> void rewrite_sigspecs(T functor);
RTLIL::Process *clone() const;