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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3

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This commit is contained in:
Clifford Wolf 2014-07-23 08:40:31 +02:00
parent 260c19ec5a
commit a8d3a68971
15 changed files with 33 additions and 47 deletions
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18
kernel/rtlil.cc
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@ -1331,13 +1331,6 @@ RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
this->offset = 0;
}
RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int width, int offset)
{
this->wire = wire;
this->width = width >= 0 ? width : wire->width;
this->offset = offset;
}
RTLIL::SigChunk RTLIL::SigChunk::grml(RTLIL::Wire *wire, int offset, int width)
{
RTLIL::SigChunk chunk;
@ -1455,13 +1448,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
check();
}
RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int width, int offset)
{
chunks_.push_back(RTLIL::SigChunk(wire, width, offset));
width_ = chunks_.back().width;
check();
}
RTLIL::SigSpec RTLIL::SigSpec::grml(RTLIL::Wire *wire, int offset, int width)
{
RTLIL::SigSpec sig;
@ -2166,7 +2152,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
std::vector<std::string> index_tokens;
sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
if (index_tokens.size() == 1)
sig.append(RTLIL::SigSpec(wire, 1, atoi(index_tokens.at(0).c_str())));
sig.append(RTLIL::SigSpec::grml(wire, atoi(index_tokens.at(0).c_str())));
else {
int a = atoi(index_tokens.at(0).c_str());
int b = atoi(index_tokens.at(1).c_str());
@ -2174,7 +2160,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
int tmp = a;
a = b, b = tmp;
}
sig.append(RTLIL::SigSpec(wire, b-a+1, a));
sig.append(RTLIL::SigSpec::grml(wire, a, b-a+1));
}
} else
sig.append(wire);

4
kernel/sigtools.h
View file

@ -144,7 +144,7 @@ struct SigPool
{
RTLIL::SigSpec sig;
for (auto &bit : bits) {
sig.append(RTLIL::SigSpec(bit.first, 1, bit.second));
sig.append(RTLIL::SigSpec::grml(bit.first, bit.second));
break;
}
return sig;
@ -154,7 +154,7 @@ struct SigPool
{
RTLIL::SigSpec sig;
for (auto &bit : bits)
sig.append(RTLIL::SigSpec(bit.first, 1, bit.second));
sig.append(RTLIL::SigSpec::grml(bit.first, bit.second));
sig.sort_and_unify();
return sig;
}