Emil J. Tywoniak
4cbc92f50f
quicklogic: add fracturable full-block dspv1 to keep vendor simulation model unchanged
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
35efe92949
quicklogic: fix dspv2 tests
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
a13b0f6b9e
quicklogic: rename dspv1 full synth_quicklogic test for clarity
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
7380cf6217
quicklogic: ql_dsp_simd add dspv1 test
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
642c313947
quicklogic: remove irrelevant comments in dspv2 test
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
9b52ba8738
quicklogic: ql_dsp_simd add dspv2 support, fix dspv1
2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
47b270a03e
synth_quicklogic: enable dspv2 tests, fix -dspv2
2025-03-11 10:35:30 +01:00
Emil J. Tywoniak
c451d8ebb9
synth_quicklogic: add -dspv2 to opt into v2 DSP blocks
2025-03-11 10:35:30 +01:00
Martin Povišer
370a033d4e
qlf_k6n10f: Start tests
2025-03-11 10:35:01 +01:00
N. Engelhardt
268a034b21
Merge pull request #4866 from YosysHQ/ql_ioff
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add IOFF inference for qlf_k6n10f
2025-03-03 14:12:09 +00:00
Emil J
b4a169527d
Merge pull request #4894 from YosysHQ/emil/abstract
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Add `abstract` pass for formal verification
2025-02-25 11:16:37 +01:00
Emil J. Tywoniak
3f60a2cc67
abstract: test -slice from:to for -init
2025-02-25 00:22:14 +01:00
Emil J. Tywoniak
3cb7054e53
abstract: test -slice for all modes, -rtlilslice for -init
2025-02-25 00:18:16 +01:00
Emil J. Tywoniak
5bd18613bb
abstract: test -init
2025-02-19 23:03:43 +01:00
Emil J. Tywoniak
34e3fcbb31
abstract: test -value
2025-02-18 17:08:45 +01:00
Emil J. Tywoniak
d3a90021ad
abstract: test -state
2025-02-18 17:08:45 +01:00
Jannis Harder
7cd822b7f5
rtlil: Add {from,to}_hdl_index methods to Wire
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In the past we had the occasional bug due to some place not handling all
4 combinations of upto/downto and zero/nonzero start_offset correctly.
2025-02-18 17:08:45 +01:00
Emil J. Tywoniak
387d0de383
abstract: -state allow partial abstraction, don't use buffer-normalized mode
2025-02-18 17:08:45 +01:00
Emil J. Tywoniak
6027030215
abstract: -value MVP, use buffer-normalized mode
2025-02-18 17:08:45 +01:00
Emil J. Tywoniak
4637fa74e3
abstract: -init MVP
2025-02-18 17:08:45 +01:00
Emil J. Tywoniak
e4ca7b8846
abstract: -state MVP
2025-02-18 17:08:45 +01:00
Krystine Sherwin
db5b76edc1
Add test for shifting by INT_MAX
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Currently resulting in CI failing on main during fsm checks which generate a circuit that simplifies to this.
2025-02-14 14:01:27 +13:00
N. Engelhardt
303a386ecc
create duplicate IOFFs if multiple output ports are connected to the same register
2025-01-31 11:28:57 +01:00
Jannis Harder
40c690b030
extract_fa: Add test case
2025-01-30 18:45:06 +01:00
N. Engelhardt
9da4fe747e
fix bus ioff inference
2025-01-28 11:23:36 +01:00
N. Engelhardt
2241a65f78
fix tests not expecting ioffs
2025-01-24 21:29:10 +01:00
N. Engelhardt
1cf8e7c7db
add ioff inference for qlf_k6n10f
2025-01-24 21:17:15 +01:00
N. Engelhardt
7e3990b681
Merge pull request #4837 from YosysHQ/json_scopinfo_opt
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write_json: add option to include $scopeinfo cells
2025-01-10 09:57:22 +00:00
N. Engelhardt
77b28442a5
emit $scopeinfo cells by default
2025-01-08 14:47:46 +01:00
Martin Povišer
ca0ace66bc
Merge pull request #4817 from povik/macc_v2-1
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macc: Stop using the B port
2025-01-08 14:42:51 +01:00
N. Engelhardt
dab7905cbe
write_json: add option to include $scopeinfo cells
2025-01-08 13:33:56 +01:00
Martin Povišer
652a1b9806
macc: Stop using the B port
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The B port is for single-bit summands. These can just as well be
represented as an additional summand on the A port (which supports
summands of arbitrary width). An upcoming `$macc_v2` cell won't be
special-casing single-bit summands in any way.
In preparation, make the following changes:
* remove the `bit_ports` field from the `Macc` helper (instead add any
single-bit summands to `ports` next to other summands)
* leave `B` empty on cells emitted from `Macc::to_cell`
2025-01-08 13:03:35 +01:00
Martin Povišer
41e4aa8f0a
Merge pull request #4819 from povik/wreduce-resign
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wreduce: Optimize signedness when possible
2025-01-06 15:27:55 +01:00
Emil J
6ab5be4a0e
Merge pull request #4814 from YosysHQ/emil/make-test-fasterer
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test: every test everywhere all at once
2024-12-18 19:02:39 +01:00
Martin Povišer
08778917db
wreduce: Optimize signedness when possible
2024-12-16 12:57:08 +01:00
Emil J. Tywoniak
6240aec433
test: restore verific handling, nicer naming
2024-12-13 10:24:47 +01:00
N. Engelhardt
378864d33b
bound attributes: handle vhdl null ranges
2024-12-12 11:42:39 +01:00
Emil J. Tywoniak
603e5eb30a
test: every test everywhere all at once
2024-12-12 01:28:36 +01:00
N. Engelhardt
03033ab6d4
add more tests for bounds attributes, fix attributes appearing in verilog
2024-12-11 16:11:02 +01:00
Martin Povišer
4bd6061709
Merge pull request #4799 from povik/wrapcell-unused
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wrapcell: Optionally track unused outputs
2024-12-10 21:16:28 +01:00
Emil J. Tywoniak
55dcf0e200
tests: fix dfflibmap test - false negative conflict multiple -liberty vs enable inference
2024-12-10 15:48:23 +01:00
Martin Povišer
48c8d70a45
wrapcell: Test check -assert post wrapping
2024-12-10 15:13:31 +01:00
Emil J
87736a2bf9
Merge pull request #4807 from YosysHQ/emil/dfflibmap-test-dffe
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dfflibmap: cover enable inference with test
2024-12-10 12:41:11 +01:00
Martin Povišer
b0708a38bf
Merge pull request #4678 from povik/tcl-rtlil-api
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Start Tcl design inspection methods
2024-12-09 15:44:58 +01:00
Emil J. Tywoniak
681b678417
dfflibmap: cover enable inference with test
2024-12-09 14:18:08 +01:00
Miodrag Milanovic
05398889ad
Add verific verilog test cases for blackboxes
2024-12-06 16:13:25 +01:00
N. Engelhardt
8b0f665cc5
add setenv pass
2024-12-06 11:25:43 +01:00
Martin Povišer
d57d21e566
wrapcell: Optionally track unused outputs
2024-12-05 18:16:53 +01:00
Martin Povišer
59a96470df
Merge pull request #4773 from povik/wrapcell
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wrapcell: Add new command
2024-12-04 11:49:51 +01:00
Martin Povišer
14ee5ce800
Merge pull request #4787 from povik/booth-macc
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booth: Map simple `$macc` instances too
2024-12-04 11:49:34 +01:00
