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synth_quicklogic: add -dspv2 to opt into v2 DSP blocks

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Emil J. Tywoniak 2025-02-25 11:29:45 +01:00 • committed by Martin Povišer
parent 370a033d4e
commit c451d8ebb9
10 changed files with 4680 additions and 24 deletions
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2
tests/arch/quicklogic/dspv2/complex_mult.ys
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@ -12,7 +12,7 @@ module top(input signed [16:0] ar, input signed [16:0] ai, input signed [16:0] b
endmodule
EOF
synth_quicklogic -family qlf_k6n10f -run :coarse
synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
check -assert
read_verilog +/quicklogic/qlf_k6n10f/dsp_sim.v
prep -top top -flatten

2
tests/arch/quicklogic/dspv2/simple.ys
View file

@ -11,7 +11,7 @@ module top(input [16:0] a, input [16:0] b, output reg [33:0] o, input clk, input
endmodule
EOF
synth_quicklogic -family qlf_k6n10f -run :coarse
synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
check
opt_clean
dump

2
tests/arch/quicklogic/dspv2/simple2.ys
View file

@ -5,7 +5,7 @@ module top(input [16:0] a, input [16:0] b, input [16:0] c, input [16:0] d, outpu
endmodule
EOF
synth_quicklogic -family qlf_k6n10f -run :coarse
synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
read_verilog +/quicklogic/qlf_k6n10f/dsp_sim.v
prep -top top -flatten
opt_clean -purge