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quicklogic: rename dspv1 full synth_quicklogic test for clarity

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Emil J. Tywoniak 2025-03-06 17:59:46 +01:00 committed by Martin Povišer
parent 7380cf6217
commit a13b0f6b9e
1 changed files with 3 additions and 3 deletions
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6
tests/arch/quicklogic/qlf_k6n10f/dsp.ys → tests/arch/quicklogic/qlf_k6n10f/dspv1_full.ys
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@ -21,7 +21,7 @@ EOF
design -save ast
proc
wreduce
#equiv_opt -async2sync -map +/quicklogic/qlf_k6n10f/dsp_sim.v synth_quicklogic -family qlf_k6n10f
#equiv_opt -async2sync -map +/quicklogic/qlf_k6n10f/dspv1_sim.v synth_quicklogic -family qlf_k6n10f
#design -load postopt
synth_quicklogic -family qlf_k6n10f
cd top
@ -114,8 +114,8 @@ always @(posedge clk) begin
end
endmodule
EOF
read_verilog +/quicklogic/qlf_k6n10f/dsp_sim.v
read_verilog +/quicklogic/qlf_k6n10f/dspv1_sim.v
hierarchy -top testbench
proc
async2sync
sim -assert -q -clock clk -n 20
sim -q -clock clk -n 20 -assert