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qlf_k6n10f: Start tests

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Martin Povišer 2025-02-20 11:30:09 +01:00
parent e1074e0e4e
commit 370a033d4e
3 changed files with 52 additions and 0 deletions
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23
tests/arch/quicklogic/dspv2/complex_mult.ys Normal file
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read_verilog <<EOF
module top(input signed [16:0] ar, input signed [16:0] ai, input signed [16:0] br, input signed [16:0] bi, output reg signed [33:0] qr, output reg signed [33:0] qi, input clk);
reg signed [33:0] rr, ri, ir, ii;
always @(posedge clk) begin
rr <= ar * br;
ri <= ar * bi;
ir <= ai * br;
ii <= ai * bi;
qr <= rr - ii;
qi <= ir + ri;
end
endmodule
EOF
synth_quicklogic -family qlf_k6n10f -run :coarse
check -assert
read_verilog +/quicklogic/qlf_k6n10f/dsp_sim.v
prep -top top -flatten
opt_clean -purge
opt -full
opt_clean -purge
check -assert
dump

17
tests/arch/quicklogic/dspv2/simple.ys Normal file
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read_verilog <<EOF
module top(input [16:0] a, input [16:0] b, output reg [33:0] o, input clk, input [2:0] j);
reg [16:0] ar;
reg [16:0] br;
always @(posedge clk) begin
ar <= a;
br <= b;
o <= {ar * br, j};
end
endmodule
EOF
synth_quicklogic -family qlf_k6n10f -run :coarse
check
opt_clean
dump

12
tests/arch/quicklogic/dspv2/simple2.ys Normal file
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read_verilog <<EOF
module top(input [16:0] a, input [16:0] b, input [16:0] c, input [16:0] d, output reg [33:0] o);
always @(*)
o <= (a * b) + (c * d);
endmodule
EOF
synth_quicklogic -family qlf_k6n10f -run :coarse
read_verilog +/quicklogic/qlf_k6n10f/dsp_sim.v
prep -top top -flatten
opt_clean -purge
dump