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quicklogic: add fracturable full-block dspv1 to keep vendor simulation model unchanged
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8 changed files with 157 additions and 20 deletions
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@ -21,13 +21,14 @@ chtype -set $mul t:$__soft_mul
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techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=10 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__QL_MUL10X9
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techmap -map +/quicklogic/qlf_k6n10f/dspv1_map.v -D USE_DSP_CFG_PARAMS=0
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read_verilog -lib +/quicklogic/qlf_k6n10f/dspv1_sim.v
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read_verilog -lib +/quicklogic/qlf_k6n10f/dspv1_sim_extra.v
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select -assert-count 2 t:dsp_t1_10x9x32_cfg_ports
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select -assert-count 0 t:dsp_t1_20x18x64_cfg_ports
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equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/dspv1_sim.v ql_dsp_simd
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select -assert-count 0 t:dsp_t1_20x18x64_cfg_ports_fracturable
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equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/dspv1_sim.v -map +/quicklogic/qlf_k6n10f/dspv1_sim_extra.v ql_dsp_simd
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design -load postopt
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select -assert-count 0 t:dsp_t1_10x9x32_cfg_ports
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select -assert-count 1 t:dsp_t1_20x18x64_cfg_ports
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select -assert-count 1 t:dsp_t1_20x18x64_cfg_ports_fracturable
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design -reset
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@ -54,10 +55,11 @@ chtype -set $mul t:$__soft_mul
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techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=10 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__QL_MUL10X9
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techmap -map +/quicklogic/qlf_k6n10f/dspv1_map.v -D USE_DSP_CFG_PARAMS=0
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read_verilog -lib +/quicklogic/qlf_k6n10f/dspv1_sim.v
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read_verilog -lib +/quicklogic/qlf_k6n10f/dspv1_sim_extra.v
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select -assert-count 2 t:dsp_t1_10x9x32_cfg_ports
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select -assert-count 0 t:dsp_t1_20x18x64_cfg_ports
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equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/dspv1_sim.v ql_dsp_simd
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select -assert-count 0 t:dsp_t1_20x18x64_cfg_ports_fracturable
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equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/dspv1_sim.v -map +/quicklogic/qlf_k6n10f/dspv1_sim_extra.v ql_dsp_simd
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design -load postopt
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select -assert-count 0 t:dsp_t1_10x9x32_cfg_ports
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select -assert-count 1 t:dsp_t1_20x18x64_cfg_ports
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select -assert-count 1 t:dsp_t1_20x18x64_cfg_ports_fracturable
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