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Code Activity
7682 commits 121 branches 59 tags 45 MiB
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743 commits

Author SHA1 Message Date
Miodrag Milanovic
487b38b124 Split latches into separete tests 2019-10-17 17:11:11 +02:00
Miodrag Milanovic
fba6229718 Fix formatting 2019-10-17 17:10:42 +02:00
Miodrag Milanovic
53bc499a90 Clean verilog code from not used define block 2019-10-17 17:10:42 +02:00
Miodrag Milanovic
d37cd267a5 Removed alu and div_mod test as agreed, ignore generated files 2019-10-17 17:10:42 +02:00
Miodrag Milanovic
a7fbc8c3fe Test per flip-flop type 2019-10-17 17:10:42 +02:00
Eddie Hung
3b44084320 Add -assert 2019-10-17 17:10:42 +02:00
Eddie Hung
8422ad3e3a Use built-in async2sync call as per #1417 2019-10-17 17:10:42 +02:00
Eddie Hung
5b7bc3ab85 Update mul test to DSP48E1 2019-10-17 17:10:02 +02:00
Eddie Hung
08bd1816e3 Update area for div_mod 2019-10-17 17:10:02 +02:00
Eddie Hung
a12801843b Add comment for lack of tristate logic pointing to #1225 2019-10-17 17:10:02 +02:00
Eddie Hung
eded90b6b4 Move $x to end as 7f0eec8 2019-10-17 17:10:02 +02:00
SergeyDegtyar
305672170b adffs test update (equiv_opt -multiclock) 2019-10-17 17:10:02 +02:00
Sergey
bb70eb977d Fix div_mod test 2019-10-17 17:10:02 +02:00
Sergey
68f9239c57 Fix div_mod test 2019-10-17 17:10:02 +02:00
Sergey
df6d0b95da Fix div_mod test 2019-10-17 17:10:02 +02:00
Sergey
c340d54657 Fix div_mod test 2019-10-17 17:10:02 +02:00
Sergey
205f52ffe5 Fix div_mod test 2019-10-17 17:10:02 +02:00
Sergey
df7fe40529 Fix div_mod test 2019-10-17 17:10:02 +02:00
SergeyDegtyar
7bc8f0c2e2 Add comment with expected behavior for latches,tribuf tests;Update adffs test 2019-10-17 17:10:02 +02:00
SergeyDegtyar
489444bcba Fix latches.ys test 2019-10-17 17:10:02 +02:00
SergeyDegtyar
6331fa5b02 Remove xilinx_ug901 tests (will be moved to yosys-tests) 2019-10-17 17:10:02 +02:00
SergeyDegtyar
757c476f62 Add smoke tests to tests/xilinx 2019-10-17 17:10:02 +02:00
SergeyDegtyar
ca7a58bcc8 Add comments for unproven cells. 2019-10-17 17:08:38 +02:00
SergeyDegtyar
2ae7dec530 Add tests for Xilinx UG901 examples 2019-10-17 17:08:38 +02:00
Clifford Wolf
e84cedfae4 Use "(id)" instead of "id" for types as temporary hack 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-14 05:24:31 +02:00
Eddie Hung
3fb604c75d Revert "Add test that is expecting to fail" 
This reverts commit c28d4b8047.
 2019-10-08 12:41:26 -07:00
Eddie Hung
cfc181cba9
Merge pull request #1432 from YosysHQ/eddie/fix1427 
Refactor peepopt_dffmux and be sensitive to \init when trimming
 2019-10-08 12:38:29 -07:00
Eddie Hung
4c89a4e642
Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2sync 
async2sync to be called by equiv_opt only when -async2sync given
 2019-10-08 10:53:44 -07:00
Eddie Hung
5c68da4150 Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf 2019-10-05 09:27:12 -07:00
Eddie Hung
045f344038 Use sat -tempinduct and comments for why equiv_opt not sufficient 2019-10-03 11:11:50 -07:00
Eddie Hung
bd5889640b Disable equiv check for ice40 latches 2019-10-03 10:45:53 -07:00
Eddie Hung
5d680590d6 Use equiv_opt -async2sync for xilinx 2019-10-03 10:30:33 -07:00
Clifford Wolf
0e05424885
Merge pull request #1422 from YosysHQ/eddie/aigmap_select 
Add -select option to aigmap
 2019-10-03 11:54:04 +02:00
David Shah
9b9d24f15b sv: Improve tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:45 +01:00
David Shah
abc155715d sv: Add test scripts for typedefs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah
af25585170 sv: Add support for memories of a typedef 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah
30d2326030 sv: Add support for memory typedefs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah
e70e4afb60 sv: Fix typedefs in packages 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah
c962951612 sv: Fix typedef parameters 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah
f6b5e47e40 sv: Switch parser to glr, prep for typedef 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
Eddie Hung
e9645c7fa7 Fix broken CI, check reset even for constants, trim rstmux 2019-10-02 21:26:26 -07:00
Eddie Hung
e4bd5aaebf Fix test 2019-10-02 18:12:25 -07:00
Eddie Hung
c6a55d948a Merge branch 'eddie/fix_sat_init' into eddie/fix1427 2019-10-02 18:07:38 -07:00
Eddie Hung
f6fabc8fda Update test 2019-10-02 18:03:45 -07:00
Eddie Hung
e730a595ee Add test 2019-10-02 18:01:41 -07:00
Eddie Hung
c28d4b8047 Add test that is expecting to fail 2019-10-02 14:52:40 -07:00
Eddie Hung
a4f2f7d23c Extend test with renaming cells with prefix too 2019-10-02 12:43:18 -07:00
Eddie Hung
369652d4b9 Add test 2019-09-30 17:20:39 -07:00
Eddie Hung
8b239ee707 Add quick test 2019-09-30 15:34:04 -07:00
whitequark
5c5881695d
Merge pull request #1406 from whitequark/connect_rpc 
rpc: new frontend
 2019-09-30 17:38:20 +00:00