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Add test

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This commit is contained in:
Eddie Hung 2019-09-30 17:20:39 -07:00
parent edc3780723
commit 369652d4b9
1 changed files with 16 additions and 0 deletions
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tests/techmap/techmap_replace.ys Normal file
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read_verilog <<EOT
module sub(input i, output o, input j);
foobar _TECHMAP_REPLACE_(i, o, j);
wire _TECHMAP_REPLACE_.asdf = i ;
endmodule
EOT
design -stash techmap
read_verilog <<EOT
module top(input i, output o);
sub s0(i, o);
endmodule
EOT
techmap -map %techmap
select -assert-any w:s0.asdf