113 commits

Author	SHA1	Message	Date
Clifford Wolf	c3e779a65f	Added $_BUF_ cell type	2014-10-03 10:12:28 +02:00
Clifford Wolf	f9a307a50b	namespace Yosys	2014-09-27 16:17:53 +02:00
Clifford Wolf	4888d61c65	Improvements in "synth" script	2014-09-18 12:57:55 +02:00
Clifford Wolf	6644e27cd4	Fixed $macc simlib model for zero-config	2014-09-16 08:19:35 +02:00
Clifford Wolf	7815f81c32	Added "synth" command	2014-09-14 16:09:06 +02:00
Clifford Wolf	923bbbeaf0	Using alumacc in techmap.v	2014-09-14 14:50:15 +02:00
Clifford Wolf	44b5bd4b63	Fixed simlib $macc model for xilinx xsim	2014-09-08 17:09:39 +02:00
Clifford Wolf	fcb46138ce	Simplified $fa undef model	2014-09-08 16:59:39 +02:00
Clifford Wolf	6dc07eb1f2	Fixes and cleanups for blackbox.v	2014-09-08 13:31:04 +02:00
Clifford Wolf	af0c8873bb	Added $lcu cell type	2014-09-08 13:31:04 +02:00
Clifford Wolf	d46bac3305	Added "$fa" cell type	2014-09-08 12:15:39 +02:00
Clifford Wolf	dd887cc025	Using maccmap for $macc and $mul techmap	2014-09-07 18:24:08 +02:00
Clifford Wolf	9329a76818	Various bug fixes (related to $macc model testing)	2014-09-06 20:30:46 +02:00
Clifford Wolf	fa64942018	Added $macc SAT model	2014-09-06 19:44:11 +02:00
Clifford Wolf	bff4706b62	Added $macc simlib model (also use as techmap rule for now)	2014-09-06 17:59:12 +02:00
Clifford Wolf	8927aa6148	Removed $bu0 cell type	2014-09-04 02:07:52 +02:00
Clifford Wolf	635b922afe	Undef-related fixes in simlib $alu model	2014-09-02 23:21:59 +02:00
Clifford Wolf	c38283dbd0	Small bug fixes in $not, $neg, and $shiftx models	2014-09-02 17:48:41 +02:00
Clifford Wolf	9923762461	Fixed "test_cell -simlib all"	2014-09-01 15:37:56 +02:00
Clifford Wolf	8649b57b6f	Added $lut support in test_cell, techmap, satgen	2014-08-31 17:43:31 +02:00
Clifford Wolf	4724d94fbc	Added $alu cell type	2014-08-30 18:59:05 +02:00
Clifford Wolf	eb571cba6a	Replaced $__alu CO/CS outputs with full-width CO output	2014-08-30 15:12:39 +02:00
Clifford Wolf	a92a68ce52	Using "via_celltype" in $mul carry-save-acc implementation	2014-08-18 14:30:20 +02:00
Clifford Wolf	6f33fc3e87	Performance fix for new $__lcu techmap rule	2014-08-18 00:27:54 +02:00
Clifford Wolf	4b3834e0cc	Replaced recursive lcu scheme with bk adder	2014-08-18 00:03:33 +02:00
Clifford Wolf	976bda7102	Multiply using a carry-save accumulator	2014-08-16 21:07:29 +02:00
Clifford Wolf	47c2637a96	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_	2014-08-16 18:29:39 +02:00
Clifford Wolf	1ddf150c35	Changes in techmap $__alu interface	2014-08-16 16:01:58 +02:00
Clifford Wolf	b64b38eea2	Renamed $lut ports to follow A-Y naming scheme	2014-08-15 14:18:40 +02:00
Clifford Wolf	f092b50148	Renamed $_INV_ cell type to $_NOT_	2014-08-15 14:11:40 +02:00
Clifford Wolf	5602cbde9f	Simplified $__arraymul techmap rule	2014-08-14 20:53:21 +02:00
Clifford Wolf	13f2f36884	RIP $safe_pmux	2014-08-14 11:39:46 +02:00
Clifford Wolf	7e758d5fbb	Added techmap support for actual lookahead carry unit	2014-08-13 18:40:57 +02:00
Clifford Wolf	9a065509ac	Preparations for lookahead ALU support in techmap.v	2014-08-13 16:36:30 +02:00
Clifford Wolf	c27120fcbc	New interface for $__alu in techmap.v	2014-08-13 13:04:28 +02:00
Clifford Wolf	312ee00c9e	Added adff2dff.v (for techmap -share_map)	2014-08-07 16:14:38 +02:00
Clifford Wolf	014a41fcf3	Implemented recursive techmap	2014-08-03 12:40:43 +02:00
Clifford Wolf	1202f7aa4b	Renamed "stdcells.v" to "techmap.v"	2014-07-31 02:32:00 +02:00
Clifford Wolf	41555cde10	Reorganized stdcells.v (no actual code change, just moved and indented stuff)	2014-07-31 02:21:06 +02:00
Clifford Wolf	2541489105	Added techmap CONSTMAP feature	2014-07-30 22:04:30 +02:00
Clifford Wolf	6c05badc43	New techmap default rules for $shr $sshr $shl $sshl	2014-07-30 18:49:12 +02:00
Clifford Wolf	2145e57ef0	Bugfix in simlib.v for iverilog	2014-07-29 19:23:31 +02:00
Clifford Wolf	397b00252d	Added $shift and $shiftx cell types (needed for correct part select behavior)	2014-07-29 16:35:13 +02:00
Clifford Wolf	b17d6531c8	Added "make PRETTY=1"	2014-07-24 17:15:01 +02:00
Clifford Wolf	f1ca93a0a3	Fixed simlib.v model for $mem	2014-07-17 16:48:36 +02:00
Clifford Wolf	dcdd5c11b4	Updated simlib to new $mem/$memwr interface	2014-07-16 11:46:40 +02:00
Clifford Wolf	7370ae01e9	Added SIMLIB_NOLUT to simlib.v	2014-04-02 21:28:33 +02:00
Clifford Wolf	e24797add0	Added SIMLIB_NOSR to simlib.v	2014-04-02 21:06:55 +02:00
Clifford Wolf	d4a1b0af5b	Added support for dlatchsr cells	2014-03-31 14:14:40 +02:00
Clifford Wolf	7aa2d746b7	Merged addition of SED makefile variable from github.com/Siesh1oo/yosys ... (see https://github.com/cliffordwolf/yosys/pull/28)	2014-03-11 14:42:58 +01:00