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New interface for $__alu in techmap.v
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Clifford Wolf
parent
f53984795d
commit
c27120fcbc
1 changed files with 74 additions and 141 deletions
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@ -266,26 +266,36 @@ module \$__fulladd (A, B, C, X, Y);
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\$_OR_ gate5 ( .A(t1), .B(t3), .Y(X) );
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endmodule
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module \$__alu (A, B, Cin, Y, Cout, Csign);
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parameter WIDTH = 1;
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module \$__alu (A, B, CI, S, Y, CO, CS);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [WIDTH-1:0] A, B;
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input Cin;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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output [WIDTH-1:0] Y;
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output Cout, Csign;
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// carry in, sub, carry out, carry sign
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input CI, S;
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output CO, CS;
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wire [WIDTH:0] carry;
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assign carry[0] = Cin;
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assign Cout = carry[WIDTH];
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assign Csign = carry[WIDTH-1];
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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wire [Y_WIDTH:0] carry;
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assign carry[0] = CI;
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assign CO = carry[Y_WIDTH];
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assign CS = carry[Y_WIDTH-1];
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genvar i;
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generate
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for (i = 0; i < WIDTH; i = i + 1) begin:V
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for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
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\$__fulladd adder (
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.A(A[i]),
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.B(B[i]),
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.A(A_buf[i]),
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.B(S ? !B_buf[i] : B_buf[i]),
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.C(carry[i]),
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.X(carry[i+1]),
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.Y(Y[i])
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@ -294,99 +304,60 @@ module \$__alu (A, B, Cin, Y, Cout, Csign);
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endgenerate
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endmodule
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`define ALU_COMMONS(_width, _ci, _s) """
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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localparam WIDTH = _width;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire alu_co, alu_cs;
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wire [WIDTH-1:0] alu_y;
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\$__alu #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(WIDTH)
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) alu (
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.A(A),
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.B(B),
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.CI(_ci),
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.S(_s),
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.Y(alu_y),
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.CO(alu_co),
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.CS(alu_cs)
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);
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wire cf, of, zf, sf;
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assign cf = !alu_co;
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assign of = alu_co ^ alu_cs;
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assign zf = ~|alu_y;
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assign sf = alu_y[WIDTH-1];
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"""
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// --------------------------------------------------------
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// Compare cells
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// --------------------------------------------------------
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module \$lt (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire carry, carry_sign;
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wire [WIDTH-1:0] A_buf, B_buf, Y_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
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\$__alu #(
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.WIDTH(WIDTH)
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) alu (
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.A(A_buf),
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.B(~B_buf),
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.Cin(1'b1),
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.Y(Y_buf),
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.Cout(carry),
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.Csign(carry_sign)
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);
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// ALU flags
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wire cf, of, zf, sf;
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assign cf = !carry;
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assign of = carry ^ carry_sign;
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assign zf = ~|Y_buf;
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assign sf = Y_buf[WIDTH-1];
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generate
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if (A_SIGNED && B_SIGNED) begin
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assign Y = of != sf;
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end else begin
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assign Y = cf;
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end
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endgenerate
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wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt_const -mux_undef -mux_bool -fine;;;";
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`ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1, 1)
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assign Y = A_SIGNED && B_SIGNED ? of != sf : cf;
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endmodule
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module \$le (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire carry, carry_sign;
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wire [WIDTH-1:0] A_buf, B_buf, Y_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
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\$__alu #(
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.WIDTH(WIDTH)
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) alu (
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.A(A_buf),
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.B(~B_buf),
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.Cin(1'b1),
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.Y(Y_buf),
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.Cout(carry),
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.Csign(carry_sign)
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);
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// ALU flags
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wire cf, of, zf, sf;
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assign cf = !carry;
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assign of = carry ^ carry_sign;
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assign zf = ~|Y_buf;
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assign sf = Y_buf[WIDTH-1];
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generate
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if (A_SIGNED && B_SIGNED) begin
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assign Y = zf || (of != sf);
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end else begin
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assign Y = zf || cf;
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end
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endgenerate
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wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt_const -mux_undef -mux_bool -fine;;;";
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`ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1, 1)
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assign Y = zf || (A_SIGNED && B_SIGNED ? of != sf : cf);
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endmodule
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@ -395,53 +366,15 @@ endmodule
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// --------------------------------------------------------
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module \$add (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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\$__alu #(
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.WIDTH(Y_WIDTH)
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) alu (
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.A(A_buf),
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.B(B_buf),
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.Cin(1'b0),
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.Y(Y)
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);
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wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt_const -mux_undef -mux_bool -fine;;;";
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`ALU_COMMONS(Y_WIDTH, 0, 0)
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assign Y = alu_y;
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endmodule
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module \$sub (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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\$__alu #(
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.WIDTH(Y_WIDTH)
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) alu (
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.A(A_buf),
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.B(~B_buf),
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.Cin(1'b1),
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.Y(Y)
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);
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wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt_const -mux_undef -mux_bool -fine;;;";
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`ALU_COMMONS(Y_WIDTH, 1, 1)
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assign Y = alu_y;
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endmodule
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