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Renamed $lut ports to follow A-Y naming scheme

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This commit is contained in:
Clifford Wolf 2014-08-15 14:18:40 +02:00
parent f092b50148
commit b64b38eea2
6 changed files with 38 additions and 39 deletions
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22
techlibs/common/simlib.v
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@ -955,13 +955,13 @@ endmodule
// --------------------------------------------------------
`ifndef SIMLIB_NOLUT
module \$lut (I, O);
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] I;
output reg O;
input [WIDTH-1:0] A;
output reg Y;
wire lut0_out, lut1_out;
@ -969,18 +969,18 @@ generate
if (WIDTH <= 1) begin:simple
assign {lut1_out, lut0_out} = LUT;
end else begin:complex
\$lut #( .WIDTH(WIDTH-1), .LUT(LUT ) ) lut0 ( .I(I[WIDTH-2:0]), .O(lut0_out) );
\$lut #( .WIDTH(WIDTH-1), .LUT(LUT >> (2**(WIDTH-1))) ) lut1 ( .I(I[WIDTH-2:0]), .O(lut1_out) );
\$lut #( .WIDTH(WIDTH-1), .LUT(LUT ) ) lut0 ( .A(A[WIDTH-2:0]), .Y(lut0_out) );
\$lut #( .WIDTH(WIDTH-1), .LUT(LUT >> (2**(WIDTH-1))) ) lut1 ( .A(A[WIDTH-2:0]), .Y(lut1_out) );
end
if (WIDTH > 0) begin:lutlogic
always @* begin
casez ({I[WIDTH-1], lut0_out, lut1_out})
3'b?11: O = 1'b1;
3'b?00: O = 1'b0;
3'b0??: O = lut0_out;
3'b1??: O = lut1_out;
default: O = 1'bx;
casez ({A[WIDTH-1], lut0_out, lut1_out})
3'b?11: Y = 1'b1;
3'b?00: Y = 1'b0;
3'b0??: Y = lut0_out;
3'b1??: Y = lut1_out;
default: Y = 1'bx;
endcase
end
end

36
techlibs/xilinx/cells.v
View file

@ -10,41 +10,41 @@ module \$_DFF_P_ (D, C, Q);
endmodule
module \$lut (I, O);
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] I;
output O;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin:lut1
LUT1 #(.INIT(LUT)) fpga_lut (.O(O),
.I0(I[0]));
LUT1 #(.INIT(LUT)) fpga_lut (.O(Y),
.I0(A[0]));
end else
if (WIDTH == 2) begin:lut2
LUT2 #(.INIT(LUT)) fpga_lut (.O(O),
.I0(I[0]), .I1(I[1]));
LUT2 #(.INIT(LUT)) fpga_lut (.O(Y),
.I0(A[0]), .I1(A[1]));
end else
if (WIDTH == 3) begin:lut3
LUT3 #(.INIT(LUT)) fpga_lut (.O(O),
.I0(I[0]), .I1(I[1]), .I2(I[2]));
LUT3 #(.INIT(LUT)) fpga_lut (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]));
end else
if (WIDTH == 4) begin:lut4
LUT4 #(.INIT(LUT)) fpga_lut (.O(O),
.I0(I[0]), .I1(I[1]), .I2(I[2]),
.I3(I[3]));
LUT4 #(.INIT(LUT)) fpga_lut (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]));
end else
if (WIDTH == 5) begin:lut5
LUT5 #(.INIT(LUT)) fpga_lut (.O(O),
.I0(I[0]), .I1(I[1]), .I2(I[2]),
.I3(I[3]), .I4(I[4]));
LUT5 #(.INIT(LUT)) fpga_lut (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]));
end else
if (WIDTH == 6) begin:lut6
LUT6 #(.INIT(LUT)) fpga_lut (.O(O),
.I0(I[0]), .I1(I[1]), .I2(I[2]),
.I3(I[3]), .I4(I[4]), .I5(I[5]));
LUT6 #(.INIT(LUT)) fpga_lut (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
end else begin:error
wire _TECHMAP_FAIL_ = 1;
end