mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 01:25:33 +00:00
Code Activity

Renamed "stdcells.v" to "techmap.v"

Browse source
This commit is contained in:
Clifford Wolf 2014-07-31 02:32:00 +02:00
parent 6ca0c569d9
commit 1202f7aa4b
9 changed files with 15 additions and 12 deletions
Download patch file Download diff file Expand all files Collapse all files

6
techlibs/common/Makefile.inc
View file

@ -5,7 +5,7 @@ techlibs/common/blackbox.v: techlibs/common/blackbox.sed techlibs/common/simlib.
$(P) cat techlibs/common/simlib.v techlibs/common/simcells.v | $(SED) -rf techlibs/common/blackbox.sed > techlibs/common/blackbox.v.new
$(Q) mv techlibs/common/blackbox.v.new techlibs/common/blackbox.v
EXTRA_TARGETS += share/simlib.v share/simcells.v share/blackbox.v share/pmux2mux.v
EXTRA_TARGETS += share/simlib.v share/simcells.v share/techmap.v share/blackbox.v share/pmux2mux.v
share/simlib.v: techlibs/common/simlib.v
$(P) mkdir -p share
@ -15,6 +15,10 @@ share/simcells.v: techlibs/common/simcells.v
$(P) mkdir -p share
$(Q) cp techlibs/common/simcells.v share/simcells.v
share/techmap.v: techlibs/common/techmap.v
$(P) mkdir -p share
$(Q) cp techlibs/common/techmap.v share/techmap.v
share/blackbox.v: techlibs/common/blackbox.v
$(P) mkdir -p share
$(Q) cp techlibs/common/blackbox.v share/blackbox.v

2
techlibs/common/simcells.v
View file

@ -21,7 +21,7 @@
*
* This verilog library contains simple simulation models for the internal
* logic cells ($_INV_ , $_AND_ , ...) that are generated by the default technology
* mapper (see "stdcells.v" in this directory) and expected by the "abc" pass.
* mapper (see "techmap.v" in this directory) and expected by the "abc" pass.
*
*/

0
techlibs/common/stdcells.v → techlibs/common/techmap.v
View file