2369 commits

Author	SHA1	Message	Date
Emil J. Tywoniak	6adc08b0e5	opt_expr: use newcelltypes	2026-03-04 12:22:14 +01:00
Emil J. Tywoniak	a61455645d	newcelltypes: init	2026-03-04 12:22:14 +01:00
Akash Levy	958f1c608a	Merge pull request #116 from Silimate/autoscope ... Autoscope	2026-03-03 20:49:13 -08:00
Akash Levy	1de7182d14	Merge pull request #114 from Silimate/vcd-fork ... Vcd fork	2026-03-03 20:48:44 -08:00
Stan Lee	7e8331dd95	greptile	2026-03-03 15:15:26 -08:00
Stan Lee	a1470e14fe	typos	2026-03-02 12:57:37 -08:00
Stan Lee	a449e6ab38	always dump available scopes	2026-03-02 12:19:09 -08:00
Stan Lee	83e05a6509	fixes	2026-03-02 12:07:59 -08:00
Stan Lee	da25b800bc	finalized	2026-03-02 11:05:44 -08:00
Stan Lee	6594ff508f	improvement	2026-03-02 00:42:34 -08:00
Akash Levy	7d96a7f73c	Update aigmap to go a lot faster using aig template cache and uniquify cache	2026-03-01 22:35:06 -08:00
Stan Lee	c459a74c13	autoscoping	2026-03-01 15:39:35 -08:00
Stan Lee	8ee71ddc7f	bugfix	2026-02-27 12:19:14 -08:00
Stan Lee	93af5a5232	in order	2026-02-27 12:17:43 -08:00
Stan Lee	c42d2c2d03	support for nested structs	2026-02-27 11:54:43 -08:00
Stan Lee	d36e2f7d17	resolve accidental change	2026-02-27 11:40:13 -08:00
Stan Lee	03ce300b49	another indent	2026-02-27 11:29:31 -08:00
Stan Lee	fa1267e0cb	fix indents	2026-02-27 11:27:37 -08:00
Stan Lee	ae3b9b74e2	ready	2026-02-27 11:25:10 -08:00
Stan Lee	48894488f1	better method for assigning fsthandles	2026-02-27 11:25:10 -08:00
Stan Lee	0aaca679ce	better but not ideal	2026-02-27 11:25:10 -08:00
Stan Lee	5bdc2d3451	working implementation that i will improvee further	2026-02-27 11:25:10 -08:00
Emil J	5f8489d36d	Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors ... equiv_induct: error on missing model	2026-02-25 15:39:31 +01:00
Akash Levy	0b46d8b201	Merge pull request #109 from Silimate/clkgate_attr ... Added is_clock_gated attr to flops created via clockgate.cc pass	2026-02-20 17:02:02 -08:00
AdvaySingh1	8f5b8cb46c	Added is_clock_gated attr to flops created via clockgate.cc pass	2026-02-20 11:34:08 -08:00
Emil J	74f7b0cf92	Merge pull request #5685 from chathhorn-galois/chathhorn/issue5684 ... Fix segfault from shift with 0-width signed arg.	2026-02-20 11:53:05 +01:00
Emil J	53509a9b2a	Merge pull request #5692 from YosysHQ/emil/modtools-fix-db-port-deletion ... modtools: fix database sanity	2026-02-20 10:49:28 +01:00
AdvaySingh1	b29514fafc	Added built in cell alongside sim support for cell	2026-02-19 11:48:35 -08:00
Emil J. Tywoniak	abc7563a35	modtools: add ModIndex unit test	2026-02-18 22:15:44 +01:00
Emil J. Tywoniak	c75d80905a	modtools: fix database sanity on wire name swap	2026-02-18 21:23:21 +01:00
Akash Levy	b7098e8383	Merge branch 'YosysHQ:main' into main	2026-02-18 09:44:25 -08:00
Gus Smith	29a270c4b6	Merge pull request #5675 from rowanG077/add-missing-celledges ... kernel/celledges: cover more cell types	2026-02-18 07:50:41 -08:00
Emil J. Tywoniak	62f19cb3a9	modtools: fix port_del db erase	2026-02-18 12:20:36 +01:00
Emil J. Tywoniak	77f64de997	satgen: move report_missing_model here from equiv.h	2026-02-16 17:01:09 +01:00
Akash Levy	5debd619e5	Add workaround for Liberty duplication	2026-02-13 06:51:42 -08:00
Akash Levy	0485576632	Revert rtlil changes	2026-02-13 04:14:14 -08:00
Akash Levy	2b247d165b	Merge from main	2026-02-13 04:14:08 -08:00
Akash Levy	b8d83c1d5b	Fix cell naming issues	2026-02-13 01:05:51 -08:00
Chris Hathhorn	1e852cef16	Fix segfault from shift with 0-width signed arg. ... Fixes #5684.	2026-02-12 22:03:42 -06:00
Gus Smith	8ab105ac28	Merge pull request #4303 from Coloquinte/sat_choice ... Infrastructure to run a Sat solver as a command	2026-02-11 06:54:53 -08:00
Rowan Goemans	b8ee50d77f	kernel/celledges: cover more cell types	2026-02-09 14:13:40 +01:00
Gus Smith	1502e23371	Set solver from scratchpad or command line	2026-02-06 19:26:32 -08:00
Akash Levy	f74ac17a5f	Undo the terrible upstream changes that break everything...	2026-02-04 22:26:06 -08:00
Akash Levy	d3ab45c2fa	Merge branch 'YosysHQ:main' into main	2026-02-04 15:53:43 -08:00
Emil J	2aa0e1d009	Merge pull request #5629 from rocallahan/remove-zero-wires ... Avoid scanning entire module in `Module::remove()` if there are no wires to remove	2026-02-04 17:44:24 +01:00
Emil J. Tywoniak	d199195785	satgen: cover $input_port	2026-02-03 18:10:29 +01:00
Akash Levy	8e5d24aa6b	Bump yosys to latest	2026-02-03 06:08:36 -08:00
Emil J	59653da599	Merge pull request #5609 from nataliakokoromyti/upstream-design-run-pass ... Add Design::run_pass()	2026-02-02 19:30:18 +01:00
Akash Levy	16087ae931	Merge from upstream	2026-01-28 18:17:50 -08:00
nella	8f6c4d40e4	Merge pull request #5623 from YosysHQ/nella/opt-dff-rewrite ... opt_dff restructure.	2026-01-28 14:41:40 +01:00