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Added built in cell alongside sim support for cell

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AdvaySingh1 2026-02-19 11:45:33 -08:00
parent 723ddd74cf
commit b29514fafc
4 changed files with 25 additions and 0 deletions
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1
kernel/celltypes.h
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@ -110,6 +110,7 @@ struct CellTypes
setup_type(ID($overwrite_tag), {ID::A, ID::SET, ID::CLR}, pool<RTLIL::IdString>());
setup_type(ID($original_tag), {ID::A}, {ID::Y});
setup_type(ID($future_ff), {ID::A}, {ID::Y});
setup_type(ID($icg), {ID::CLK, ID::EN, ID::SE}, {ID::GCLK}, false, false, true);
setup_type(ID($scopeinfo), {}, {});
setup_type(ID($input_port), {}, {ID::Y});
setup_type(ID($connect), {ID::A, ID::B}, {});

3
kernel/constids.inc
View file

@ -221,6 +221,7 @@ X($future_ff)
X($ge)
X($get_tag)
X($gt)
X($icg)
X($initstate)
X($input)
X($input_port)
@ -488,6 +489,7 @@ X(FTCP_N)
X(FTDCP)
X(FULL)
X(G)
X(GCLK)
X(GP_DFF)
X(GP_DFFI)
X(GP_DFFR)
@ -720,6 +722,7 @@ X(SB_RAM40_4KNR)
X(SB_RAM40_4KNRNW)
X(SB_RAM40_4KNW)
X(SD)
X(SE)
X(SEL_MASK)
X(SEL_PATTERN)
X(SET)

9
kernel/rtlil.cc
View file

@ -2083,6 +2083,15 @@ namespace {
return;
}
if (cell->type == ID($icg)) {
port(ID::CLK, 1);
port(ID::EN, 1);
port(ID::SE, 1);
port(ID::GCLK, 1);
check_expected();
return;
}
if (cell->type == ID($dffsr)) {
param_bool(ID::CLK_POLARITY);
param_bool(ID::SET_POLARITY);