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https://github.com/YosysHQ/yosys
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autoscoping
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parent
0b46d8b201
commit
c459a74c13
4 changed files with 114 additions and 8 deletions
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@ -280,3 +280,77 @@ std::string FstData::valueOf(fstHandle signal)
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}
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return past_data[signal];
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}
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// Auto-discover scope from FST by finding the top module
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std::string FstData::autoScope(Module *topmod) {
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log("Auto-discovering scope from file...\n");
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std::string top = RTLIL::unescape_id(topmod->name);
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// Option 1 - Instance based scope matching
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// Will fail if the DUT instance name != the top module name
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log("Trying instance-based scope matching...\n");
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for (const auto& var : vars) {
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// Check if this scope ends with our top module
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log_debug("Checking scope: %s\n", var.scope.c_str());
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if (var.scope == top ||
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var.scope.find("." + top) != std::string::npos) {
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// Extract the full path up to (and including) the top module
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size_t pos = var.scope.find(top);
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if (pos != std::string::npos) {
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return var.scope.substr(0, pos + top.length());
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}
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}
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}
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// Option 2 - Post based scope matching
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// Matches based on exact port name matching of the top module
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log("Trying port-based scope matching...\n");
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// Map port name to their bit widths (RTL reference point)
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dict<std::string, int> ports;
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for (auto wire : topmod->wires()) {
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if (wire->port_input || wire->port_output) {
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ports[RTLIL::unescape_id(wire->name)] = wire->width;
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}
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}
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// For each scope, track which ports were found with matching width
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// (VCD reference point)
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dict<std::string, std::set<std::string>> scope_found_ports;
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for (const auto& var : vars) {
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// Strip array '[]' notation from variable name
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std::string var_name = var.name;
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size_t bracket = var_name.find('[');
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if (bracket != std::string::npos) {
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var_name = var_name.substr(0, bracket);
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}
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// Check if this variable name matches one of our port names
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if (ports.count(var_name)) {
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// Also check if width matches
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if (ports[var_name] == var.width) {
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scope_found_ports[var.scope].insert(var_name);
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}
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}
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}
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// Compare RTl and VCD references and find an exact match
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for (const auto& entry : scope_found_ports) {
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const std::string& scope = entry.first;
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const std::set<std::string>& found = entry.second;
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// Check if all port names exist in this scope
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if (found.size() == ports.size()) {
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log("Auto-discovered scope: %s (matched all %d ports by name)\n",
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scope.c_str(), (int)ports.size());
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return scope;
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}
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}
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// No match found
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log_warning("Could not auto-discover scope for module '%s'...\n",
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RTLIL::unescape_id(topmod->name).c_str());
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return "";
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}
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@ -57,6 +57,7 @@ class FstData
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dict<int,fstHandle> getMemoryHandles(std::string name);
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double getTimescale() { return timescale; }
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const char *getTimescaleString() { return timescale_str.c_str(); }
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std::string autoScope(Module *topmod);
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private:
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void extractVarNames();
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