2452 commits

Author	SHA1	Message	Date
Miodrag Milanovic	2bc46e77c8	Converted blif tests	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	1231bd5397	Convert memories tests	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	5a06a79c0c	Correctly handle errors	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	2a8d369be3	Document not covered	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	1bfb95513c	Convert autotest script wrapper	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	474d0d7b2e	cleanup	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	8953007483	Use generic testing on few more places	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	f96fa5ff00	cleanup	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	8ff28a2a86	add prep	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	336a06d091	Add common.mk	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	c04d724337	report on summary	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	45bb0413bf	Look for all result files	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	b361569abf	Save results, and create summary and report	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	ced2521b03	Convert gen-tests shell script to python	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	a2e1fbcfc6	Enabled realmath that was disabled for some reason	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	2f9e35acb8	Fix deprecation warning	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	712ce93501	Clean some seed-tests outputs	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	999255e40c	Clean some seed-tests outputs	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	2774671346	Cleanup for abcopt-tests	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	fc55f16fae	Ignore some generated files	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	3c2adfb523	Do not write to console for makefile-tests	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	8f7e5e9449	Make sure targets are built for tests	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	5494000fd7	Move clean for tests in proper Makefile	2026-04-16 11:00:44 +02:00
Miodrag Milanovic	c99855535a	Split vanilla-test to separate Makefile	2026-04-16 11:00:44 +02:00
nella	fc71719e6e	Rename csa_tree to arith_tree.	2026-04-13 12:48:05 +02:00
nella	c3c577f333	Fix test cases.	2026-04-13 12:48:05 +02:00
nella	42c309347b	Clarify.	2026-04-13 12:48:05 +02:00
nella	4f4c820f73	Cleaned up CSA tests.	2026-04-13 12:48:05 +02:00
nella	9cc2e7d95e	rm misc comments.	2026-04-13 12:48:05 +02:00
nella	9dc408eea7	CSA add alumacc related tests.	2026-04-13 12:48:05 +02:00
nella	fc9adae9a2	Consolidate csa tests.	2026-04-13 12:48:05 +02:00
nella	ab1c423692	Tighten csa tests.	2026-04-13 12:48:05 +02:00
nella	cfee6bb4af	Add more robsutness tests.	2026-04-13 12:48:05 +02:00
nella	6b0caedcdd	Add chain tests and tighten synthesis assertions for csa.	2026-04-13 12:48:05 +02:00
nella	7183016910	Edge case tests.	2026-04-13 12:48:05 +02:00
nella	1a4a41812c	Add csa synth tests.	2026-04-13 12:48:05 +02:00
nella	4c4c5cf15a	Add structural tests for csa_tree.	2026-04-13 12:48:05 +02:00
Emil J	86448c0001	Merge pull request #5655 from YosysHQ/emil/dffsr-sr-priority-undef ... Undefine set&reset behavior of $dffsr	2026-04-08 14:22:34 +00:00
Emil J	cede13a742	Merge pull request #5765 from YosysHQ/emil/muxpack-wide-port ... muxpack: fix wide Y port handling	2026-03-31 10:49:39 +00:00
Gus Smith	6a5fea1b27	Regression test for #5765	2026-03-30 08:59:28 -07:00
Miodrag Milanovic	417e871b06	Fix tests due to ABC improvements	2026-03-30 15:23:27 +01:00
Miodrag Milanović	cc915b4c76	Merge pull request #5717 from zaun/latch-support ... gowin: add hardware latch support (DL/DLN/DLC/DLP variants)	2026-03-23 16:51:30 +00:00
Emil J	7b2ab9b245	Merge pull request #5763 from YosysHQ/emil/c-slow-init ... genrtlil: fast memory initialization	2026-03-23 10:21:21 +00:00
Emil J. Tywoniak	12b443e71c	dfflibmap: consistent clk2fflogic usage in test	2026-03-19 19:48:25 +01:00
Emil J	9746bd3897	Merge pull request #5724 from abhinavputhran/fix/setundef-respect-selection ... setundef: respect selection for cells, processes, and connections	2026-03-18 22:53:06 +00:00
Emil J. Tywoniak	27737c6e2e	rtlil: add remove2 unit test	2026-03-18 23:33:35 +01:00
Lofty	c4cc53a72e	synth: fix after abc -fast removal	2026-03-18 17:59:58 +01:00
Emil J	c8f715fed8	Merge pull request #5664 from rocallahan/parallel-opt-clean ... Parallelize `opt_clean` pass	2026-03-16 09:52:34 +00:00
abhinavputhran	314d01b35f	changed rtlil to verilog. setundef_selection_ff stays rtlil because we use specific cell names if write in verilog yosys assign name that can change	2026-03-08 20:14:03 -04:00
abhinavputhran	47c2257f82	setundef: more tests! and wire selection in -init mode	2026-03-08 19:41:31 -04:00