Stefan Biereigel
c5fe04acfd
remove port direction workaround from test case
2019-05-27 18:10:39 +02:00
Eddie Hung
f3e86e06e6
Fix init
2019-05-24 18:43:26 -07:00
Eddie Hung
e1cb1bb948
Fix typos
2019-05-24 18:34:27 -07:00
Eddie Hung
d15da4bc11
Add more tests
2019-05-24 18:33:18 -07:00
Eddie Hung
4bd9465ed3
Call proc
2019-05-24 18:32:02 -07:00
Eddie Hung
f0c6b73b72
Fix duplicate driver
2019-05-24 17:44:57 -07:00
Eddie Hung
68359bcd6f
Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux
2019-05-23 13:37:53 -07:00
Eddie Hung
47f9ea142f
Add opt_rmdff tests
2019-05-23 11:26:38 -07:00
Stefan Biereigel
c2caf85f7c
add simple test case for wand/wor
2019-05-23 13:57:27 +02:00
Eddie Hung
fb09c6219b
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-21 14:21:00 -07:00
Maciej Kurc
1f52332b8d
Added tests for Verilog frontent for attributes on parameters and localparams
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-05-16 12:53:43 +02:00
Clifford Wolf
b7ec698d40
Add test case from #997
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-07 19:58:04 +02:00
Clifford Wolf
752553d8e9
Merge pull request #946 from YosysHQ/clifford/specify
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Add specify parser
2019-05-06 20:57:15 +02:00
Clifford Wolf
1706798f4e
Merge pull request #975 from YosysHQ/clifford/fix968
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Re-enable "final loop assignment" feature and fix opt_clean warnings
2019-05-06 20:53:38 +02:00
Clifford Wolf
7bab7b3d49
Merge pull request #871 from YosysHQ/verific_import
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Improve verific -chparam and add hierarchy -chparam
2019-05-06 20:51:59 +02:00
Clifford Wolf
d97c644bc1
Add tests/various/chparam.sh
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-06 16:03:15 +02:00
Clifford Wolf
d187be39d6
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968
2019-05-06 15:41:13 +02:00
Clifford Wolf
8c6e94d57c
Improve tests/various/specify.ys
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-06 12:26:15 +02:00
Eddie Hung
554c58715a
More testing
2019-05-03 15:54:25 -07:00
Eddie Hung
bfb8b3018b
Fix spacing
2019-05-03 15:42:02 -07:00
Eddie Hung
09841c2ac1
Add quick-and-dirty specify tests
2019-05-03 15:35:26 -07:00
Eddie Hung
1e5f072c05
iverilog with simcells.v as well
2019-05-03 14:03:51 -07:00
Clifford Wolf
373b236108
Merge pull request #969 from YosysHQ/clifford/pmgenstuff
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Improve pmgen, Add "peepopt" pass with shift-mul pattern
2019-05-03 20:39:50 +02:00
Clifford Wolf
71ede7cb05
Merge pull request #976 from YosysHQ/clifford/fix974
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Fix width detection of memory access with bit slice
2019-05-03 15:29:44 +02:00
Clifford Wolf
d2aa123226
Fix typo in tests/svinterfaces/runone.sh
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-03 14:40:51 +02:00
Udi Finkelstein
ac10e7d96d
Initial implementation of elaboration system tasks
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(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.
2019-05-03 03:10:43 +03:00
Eddie Hung
8829cba901
Merge remote-tracking branch 'origin/clifford/pmgenstuff' into xc7mux
2019-05-02 11:25:34 -07:00
Eddie Hung
5cd19b52da
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-02 10:44:59 -07:00
Jakob Wenzel
98ffe5fb00
fail svinterfaces testcases on yosys error exit
2019-05-02 09:52:30 +02:00
Jim Lawson
38f5424f92
Fix #938 - Crash occurs in case when use write_firrtl command
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Add missing memory initialization.
Sanity-check memory parameters.
Add Cell pointer to memory object (for error reporting).
2019-05-01 13:16:01 -07:00
Clifford Wolf
6bbe2fdbf3
Add splitcmplxassign test case and silence splitcmplxassign warning
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 10:01:54 +02:00
Clifford Wolf
e5cb9435a0
Add additional test cases for for-loops
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 09:32:07 +02:00
Clifford Wolf
b515fd2d25
Add peepopt_muldiv, fixes #930
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 11:25:15 +02:00
Eddie Hung
0f1ba94924
Remove split_shiftx tests
2019-04-26 19:45:47 -07:00
Eddie Hung
880652283c
Merge remote-tracking branch 'origin/eddie/split_shiftx' into xc7mux
2019-04-25 18:52:20 -07:00
Eddie Hung
0eb7150a57
Add test
2019-04-25 18:08:05 -07:00
Eddie Hung
eec314e262
Remove topo sort no-loop assertion, with test
2019-04-24 21:06:53 -07:00
Eddie Hung
bfd71e0990
Fix abc9 with (* keep *) wires
2019-04-23 16:11:14 -07:00
Eddie Hung
4883391b63
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 11:19:52 -07:00
Clifford Wolf
a80e74dc20
Updaye pmux2shiftx test
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 16:17:43 +02:00
Clifford Wolf
b40af877f3
Merge pull request #909 from zachjs/master
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support repeat loops with constant repeat counts outside of constant functions
2019-04-22 08:51:34 +02:00
Clifford Wolf
a98b171814
Merge pull request #944 from YosysHQ/clifford/pmux2shiftx
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Add pmux2shiftx command
2019-04-22 08:39:37 +02:00
Eddie Hung
42a6e0b0b9
Merge remote-tracking branch 'origin/clifford/libwb' into xaig
2019-04-21 14:49:18 -07:00
Clifford Wolf
d38f0c1a96
Fix tests
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-21 11:40:20 +02:00
Eddie Hung
caec7f9d2c
Merge remote-tracking branch 'origin/master' into xaig
2019-04-20 12:23:49 -07:00
Clifford Wolf
b3a3e08e38
Improve "pmux2shiftx"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 02:03:44 +02:00
Clifford Wolf
37728520a6
Improvements in "pmux2shiftx"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 01:15:48 +02:00
Eddie Hung
59c993e437
Select to find union of both sets on stack
2019-04-19 15:47:53 -07:00
Clifford Wolf
0070184ea9
Improvements in pmux2shiftx
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 00:38:25 +02:00
Clifford Wolf
4c831d72ef
Add test for pmux2shiftx
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 00:38:25 +02:00
