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Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968

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This commit is contained in:
Clifford Wolf 2019-05-06 15:41:13 +02:00
commit d187be39d6
35 changed files with 788 additions and 291 deletions
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22
tests/memories/firrtl_938.v Normal file
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@ -0,0 +1,22 @@
module top
(
input [7:0] data_a,
input [6:1] addr_a,
input we_a, clk,
output reg [7:0] q_a
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
q_a <= ram[addr_a];
end
endmodule

22
tests/simple/mem2reg.v
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@ -92,3 +92,25 @@ module mem2reg_test5(input ctrl, output out);
assign out = bar[foo[0]];
endmodule
// ------------------------------------------------------
module mem2reg_test6 (din, dout);
input wire [3:0] din;
output reg [3:0] dout;
reg [1:0] din_array [1:0];
reg [1:0] dout_array [1:0];
always @* begin
din_array[0] = din[0 +: 2];
din_array[1] = din[2 +: 2];
dout_array[0] = din_array[0];
dout_array[1] = din_array[1];
{dout_array[0][1], dout_array[0][0]} = dout_array[0][0] + dout_array[1][0];
dout[0 +: 2] = dout_array[0];
dout[2 +: 2] = dout_array[1];
end
endmodule

9
tests/simple/peepopt.v Normal file
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@ -0,0 +1,9 @@
module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
assign o = i[s*W+:W];
endmodule
module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
wire [3:0] t;
assign t = i * 3;
assign o = t / 3;
endmodule

1
tests/simple/xfirrtl
View file

@ -16,6 +16,7 @@ operators.v $pow
partsel.v drops modules
process.v drops modules
realexpr.v drops modules
retime.v Initial value (11110101) for (retime_test.ff) not supported
scopes.v original verilog issues ( -x where x isn't declared signed)
sincos.v $adff
specify.v no code (empty module generates error

8
tests/svinterfaces/runone.sh
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@ -11,13 +11,13 @@ echo "" > $STDERRFILE
echo -n "Test: ${TESTNAME} -> "
$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE >> $STDERRFILE
$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE >> $STDERRFILE
set -e
$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE 2>> $STDERRFILE
$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE 2>> $STDERRFILE
rm -f a.out reference_result.txt dut_result.txt
set -e
iverilog -g2012 ${TESTNAME}_syn.v
iverilog -g2012 ${TESTNAME}_ref_syn.v

3
tests/tools/autotest.sh
View file

@ -147,7 +147,8 @@ do
fi
if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs \
"$toolsdir"/../../techlibs/common/simlib.v
"$toolsdir"/../../techlibs/common/simlib.v \
"$toolsdir"/../../techlibs/common/simcells.v
if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
test_count=0