mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 19:52:31 +00:00
Code Activity

More testing

Browse source
This commit is contained in:
Eddie Hung 2019-05-03 15:54:25 -07:00
parent bfb8b3018b
commit 554c58715a
2 changed files with 5 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

2
tests/various/specify.v
View file

@ -24,5 +24,7 @@ module test2 (
`define T_rise 1
`define T_fall 2
(A => Q) = (`T_rise,`T_fall);
//(B => Q) = (`T_rise+`T_fall)/2.0;
(B => Q) = 1.5;
endspecify
endmodule

5
tests/various/specify.ys
View file

@ -5,7 +5,7 @@ select t:$specify2 -assert-count 0
select t:$specify3 -assert-count 1
select t:$specrule -assert-count 2
cd test2
select t:$specify2 -assert-count 1
select t:$specify2 -assert-count 2
select t:$specify3 -assert-count 0
select t:$specrule -assert-count 0
write_verilog specify.out
@ -17,9 +17,10 @@ select t:$specify2 -assert-count 0
select t:$specify3 -assert-count 1
select t:$specrule -assert-count 2
cd test2
select t:$specify2 -assert-count 1
select t:$specify2 -assert-count 2
select t:$specify3 -assert-count 0
select t:$specrule -assert-count 0
design -stash gate
# TODO: How to check $specify and $specrule-s are equivalent?
# Otherwise, need more select statements to check parameter values are as expected?