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Add splitcmplxassign test case and silence splitcmplxassign warning

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Clifford Wolf 2019-05-01 10:01:54 +02:00
parent 3b6a02d3a7
commit 6bbe2fdbf3
2 changed files with 23 additions and 0 deletions
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22
tests/simple/mem2reg.v
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@ -92,3 +92,25 @@ module mem2reg_test5(input ctrl, output out);
assign out = bar[foo[0]];
endmodule
// ------------------------------------------------------
module mem2reg_test6 (din, dout);
input wire [3:0] din;
output reg [3:0] dout;
reg [1:0] din_array [1:0];
reg [1:0] dout_array [1:0];
always @* begin
din_array[0] = din[0 +: 2];
din_array[1] = din[2 +: 2];
dout_array[0] = din_array[0];
dout_array[1] = din_array[1];
{dout_array[0][1], dout_array[0][0]} = dout_array[0][0] + dout_array[1][0];
dout[0 +: 2] = dout_array[0];
dout[2 +: 2] = dout_array[1];
end
endmodule