mirror of
https://github.com/YosysHQ/yosys
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Merge remote-tracking branch 'origin/master' into xc7mux
This commit is contained in:
Eddie Hung
commit
fb09c6219b
56 changed files with 1811 additions and 487 deletions
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@ -40,3 +40,15 @@ module dff1a_test(n1, n1_inv, clk);
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n1 <= n1_inv;
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assign n1_inv = ~n1;
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endmodule
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module dff_test_997 (y, clk, wire4);
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// https://github.com/YosysHQ/yosys/issues/997
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output wire [1:0] y;
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input clk;
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input signed wire4;
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reg [1:0] reg10 = 0;
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always @(posedge clk) begin
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reg10 <= wire4;
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end
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assign y = reg10;
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endmodule
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25
tests/simple/forloops.v
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25
tests/simple/forloops.v
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@ -0,0 +1,25 @@
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module forloops01 (input clk, a, b, output reg [3:0] p, q, x, y);
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integer k;
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always @(posedge clk) begin
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for (k=0; k<2; k=k+1)
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p[2*k +: 2] = {a, b} ^ {2{k}};
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x <= k + {a, b};
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end
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always @* begin
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for (k=0; k<4; k=k+1)
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q[k] = {~a, ~b, a, b} >> k[1:0];
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y = k - {a, b};
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end
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endmodule
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module forloops02 (input clk, a, b, output reg [3:0] q, x, output [3:0] y);
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integer k;
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always @* begin
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for (k=0; k<4; k=k+1)
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q[k] = {~a, ~b, a, b} >> k[1:0];
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end
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always @* begin
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x = k + {a, b};
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end
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assign y = k - {a, b};
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endmodule
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11
tests/simple/localparam_attr.v
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11
tests/simple/localparam_attr.v
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@ -0,0 +1,11 @@
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module uut_localparam_attr (I, O);
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(* LOCALPARAM_ATTRIBUTE = "attribute_content" *)
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localparam WIDTH = 1;
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input wire [WIDTH-1:0] I;
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output wire [WIDTH-1:0] O;
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assign O = I;
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endmodule
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@ -92,3 +92,25 @@ module mem2reg_test5(input ctrl, output out);
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assign out = bar[foo[0]];
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endmodule
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// ------------------------------------------------------
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module mem2reg_test6 (din, dout);
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input wire [3:0] din;
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output reg [3:0] dout;
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reg [1:0] din_array [1:0];
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reg [1:0] dout_array [1:0];
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always @* begin
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din_array[0] = din[0 +: 2];
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din_array[1] = din[2 +: 2];
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dout_array[0] = din_array[0];
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dout_array[1] = din_array[1];
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{dout_array[0][1], dout_array[0][0]} = dout_array[0][0] + dout_array[1][0];
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dout[0 +: 2] = dout_array[0];
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dout[2 +: 2] = dout_array[1];
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end
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endmodule
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11
tests/simple/param_attr.v
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11
tests/simple/param_attr.v
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@ -0,0 +1,11 @@
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module uut_param_attr (I, O);
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(* PARAMETER_ATTRIBUTE = "attribute_content" *)
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parameter WIDTH = 1;
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input wire [WIDTH-1:0] I;
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output wire [WIDTH-1:0] O;
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assign O = I;
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endmodule
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@ -11,13 +11,13 @@ echo "" > $STDERRFILE
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echo -n "Test: ${TESTNAME} -> "
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$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE >> $STDERRFILE
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$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE >> $STDERRFILE
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set -e
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$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE 2>> $STDERRFILE
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$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE 2>> $STDERRFILE
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rm -f a.out reference_result.txt dut_result.txt
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set -e
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iverilog -g2012 ${TESTNAME}_syn.v
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iverilog -g2012 ${TESTNAME}_ref_syn.v
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@ -147,7 +147,8 @@ do
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fi
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if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
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compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs \
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"$toolsdir"/../../techlibs/common/simlib.v
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"$toolsdir"/../../techlibs/common/simlib.v \
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"$toolsdir"/../../techlibs/common/simcells.v
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if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
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test_count=0
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52
tests/various/chparam.sh
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52
tests/various/chparam.sh
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@ -0,0 +1,52 @@
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#!/bin/bash
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trap 'echo "ERROR in chparam.sh" >&2; exit 1' ERR
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cat > chparam1.sv << "EOT"
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module top #(
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parameter [31:0] X = 0
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) (
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input [31:0] din,
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output [31:0] dout
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);
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assign dout = X-din;
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endmodule
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module top_props #(
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parameter [31:0] X = 0
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) (
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input [31:0] dout
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);
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always @* assert (dout != X);
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endmodule
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bind top top_props #(.X(123456789)) props (.*);
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EOT
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cat > chparam2.sv << "EOT"
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module top #(
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parameter [31:0] X = 0
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) (
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input [31:0] din,
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output [31:0] dout
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);
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assign dout = X-din;
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always @* assert (dout != 123456789);
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endmodule
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EOT
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if ../../yosys -q -p 'verific -sv chparam1.sv'; then
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../../yosys -q -p 'verific -sv chparam1.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
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-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
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-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
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../../yosys -q -p 'verific -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
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-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
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-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
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fi
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../../yosys -q -p 'read_verilog -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
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-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
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-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
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rm chparam1.sv
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rm chparam2.sv
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30
tests/various/specify.v
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30
tests/various/specify.v
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@ -0,0 +1,30 @@
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module test (
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input EN, CLK,
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input [3:0] D,
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output reg [3:0] Q
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);
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always @(posedge CLK)
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if (EN) Q <= D;
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specify
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if (EN) (CLK *> (Q : D)) = (1, 2:3:4);
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$setup(D, posedge CLK &&& EN, 5);
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$hold(posedge CLK, D &&& EN, 6);
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endspecify
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endmodule
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module test2 (
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input A, B,
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output Q
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);
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xor (Q, A, B);
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specify
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//specparam T_rise = 1;
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//specparam T_fall = 2;
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`define T_rise 1
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`define T_fall 2
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(A => Q) = (`T_rise,`T_fall);
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//(B => Q) = (`T_rise+`T_fall)/2.0;
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(B => Q) = 1.5;
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endspecify
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endmodule
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56
tests/various/specify.ys
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56
tests/various/specify.ys
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@ -0,0 +1,56 @@
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read_verilog -specify specify.v
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prep
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cd test
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select t:$specify2 -assert-count 0
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select t:$specify3 -assert-count 1
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select t:$specrule -assert-count 2
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cd test2
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select t:$specify2 -assert-count 2
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select t:$specify3 -assert-count 0
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select t:$specrule -assert-count 0
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cd
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write_verilog specify.out
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design -stash gold
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read_verilog -specify specify.out
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prep
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cd test
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select t:$specify2 -assert-count 0
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select t:$specify3 -assert-count 1
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select t:$specrule -assert-count 2
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cd test2
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select t:$specify2 -assert-count 2
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select t:$specify3 -assert-count 0
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select t:$specrule -assert-count 0
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cd
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design -stash gate
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design -copy-from gold -as gold test
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design -copy-from gate -as gate test
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rename -hide
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rename -enumerate -pattern A_% t:$specify3
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rename -enumerate -pattern B_% t:$specrule r:TYPE=$setup %i
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rename -enumerate -pattern C_% t:$specrule r:TYPE=$hold %i
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select n:A_* -assert-count 2
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select n:B_* -assert-count 2
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select n:C_* -assert-count 2
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equiv_make gold gate equiv
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hierarchy -top equiv
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equiv_struct
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equiv_induct -seq 5
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equiv_status -assert
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design -reset
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design -copy-from gold -as gold test2
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design -copy-from gate -as gate test2
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rename -hide
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rename -enumerate -pattern A_% t:$specify2 r:T_RISE_TYP=1 %i
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rename -enumerate -pattern B_% t:$specify2 n:A_* %d
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select n:A_* -assert-count 2
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select n:B_* -assert-count 2
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equiv_make gold gate equiv
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hierarchy -top equiv
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equiv_struct
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equiv_induct -seq 5
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equiv_status -assert
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design -reset
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