3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 00:55:32 +00:00

Improvements in pmux2shiftx

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-04-19 23:37:11 +02:00
parent 4c831d72ef
commit 0070184ea9
3 changed files with 36 additions and 33 deletions

View file

@ -1,28 +1,34 @@
module pmux2shiftx_test (
input [2:0] S1,
input [5:0] S2,
input [9:0] A, B, C, D, D, E, F,
input [9:0] G, H, I, J, K, L, M, N,
input [1:0] S3,
input [9:0] A, B, C, D, D, E, F, G, H,
input [9:0] I, J, K, L, M, N, O, P, Q,
output reg [9:0] X
);
always @* begin
case (S1)
3'd0: X = A;
3'd1: X = B;
3'd2: X = C;
3'd3: X = D;
3'd4: X = E;
3'd5: X = F;
3'd6: X = G;
3'd7: X = H;
3'd 0: X = A;
3'd 1: X = B;
3'd 2: X = C;
3'd 3: X = D;
3'd 4: X = E;
3'd 5: X = F;
3'd 6: X = G;
3'd 7: X = H;
endcase
case (S2)
6'd46: X = I;
6'd47: X = J;
6'd48: X = K;
6'd52: X = L;
6'd53: X = M;
6'd54: X = N;
6'd 45: X = I;
6'd 47: X = J;
6'd 49: X = K;
6'd 55: X = L;
6'd 57: X = M;
6'd 59: X = N;
endcase
case (S3)
2'd 1: X = O;
2'd 2: X = P;
2'd 3: X = Q;
endcase
end
endmodule

View file

@ -2,13 +2,17 @@ read_verilog pmux2shiftx.v
prep
design -save gold
pmux2shiftx
pmux2shiftx -density 70 50
opt
stat
# show -width
select -assert-count 1 t:$mux
select -assert-count 1 t:$shift
select -assert-count 2 t:$shiftx
select -assert-count 1 t:$sub
select -assert-count 2 t:$mux
select -assert-count 2 t:$shift
select -assert-count 3 t:$shiftx
design -stash gate
design -import gold -as gold