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1451 commits

Author SHA1 Message Date
Emil J. Tywoniak fbdfff168b placement new, fix empty probably 2024-06-17 10:53:08 +02:00
Emil J. Tywoniak 65d50db4ef 100% 2024-06-14 17:26:48 +02:00
Emil J. Tywoniak eeb15ea2a2 73% 2024-06-13 22:50:21 +02:00
Emil J. Tywoniak 4c9f68216a tiny fix 2024-06-13 21:37:22 +02:00
Emil J. Tywoniak 866b7a7121 conns and params from dict, oldcell no longer attrobject 2024-06-13 21:34:42 +02:00
Emil J. Tywoniak 193a43e82c erase, clear, fork replace, idk 2024-06-13 20:31:11 +02:00
Emil J. Tywoniak cc10ef7019 silly compat file 2024-06-13 18:35:01 +02:00
Emil J. Tywoniak 61cf4b6fb6 look at all those chickens 2024-06-13 14:27:11 +02:00
Emil J. Tywoniak 8bdcc6987b consty stuff 2024-06-13 12:55:52 +02:00
Emil J. Tywoniak 36289ab208 consty stuff 2024-06-13 12:35:31 +02:00
Emil J. Tywoniak 2d6c45469f clean, not backtracking 2024-06-12 19:37:45 +02:00
Emil J. Tywoniak 33987d975e dead end, backtracking 2024-06-12 19:30:55 +02:00
Emil J. Tywoniak 919e2103c9 references - breaking 2024-06-12 19:12:01 +02:00
Emil J. Tywoniak 1c2fb078eb iterator hell 2024-06-12 13:27:22 +02:00
Emil J. Tywoniak 33910bcf82 iterator hell 2024-06-12 13:12:55 +02:00
Emil J. Tywoniak d7251df9a9 wip 2024-06-11 00:06:52 +02:00
Emil J. Tywoniak c0a51c8a52 wip 2024-06-10 19:05:33 +02:00
Emil J. Tywoniak 930a9f64ee add functions to new cell 2024-06-10 18:51:38 +02:00
Emil J. Tywoniak 2213b5d66d add functions to new cell 2024-06-10 18:51:29 +02:00
Emil J. Tywoniak 8403eee59b iterators 2024-06-10 18:48:09 +02:00
Emil J. Tywoniak e243968406 delete conn iter attempt 2024-06-10 11:48:28 +02:00
Emil J. Tywoniak 277c10e127 oldcell 2024-06-10 11:06:37 +02:00
Emil J. Tywoniak b85062fcec fix stuff, don't strip 2024-06-05 22:21:31 +02:00
Emil J. Tywoniak 60bf00ea79 tracy: frame pointer, track memory allocations 2024-05-31 12:35:31 +02:00
Emil J. Tywoniak 0fb3f3a78e tracy: init, zones per pass execute method, pointer-colored 2024-05-28 23:51:17 +02:00
Martin Povišer fc82251105 techmap: Support dynamic cell types 2024-05-03 13:33:28 +02:00
KrystalDelusion c3ae33da33
Merge pull request #4285 from YosysHQ/typo_fixup
Typo fixing
2024-04-25 09:54:48 +12:00
Martin Povišer 178eceb32d rtlil: Replace the packed SigSpec::extract impl 2024-04-22 16:23:51 +02:00
Jannis Harder 0d30a4d479 rtlil: Add packed extract implementation for SigSpec
Previously `extract` on a `SigSpec` would always unpack it. Since a
significant amount of `SigSpec`s have one or few chunks, it's worth
having a dedicated implementation.

This is especially true, since the RTLIL frontend calls into this for
every `wire [lhs:rhs]` slice, making this `extract` take up 40% when
profiling `read_rtlil` with one of the largest coarse grained RTLIL
designs I had on hand.

With this change the `read_rtlil` profile looks like I would expect it
to look like, but I noticed that a lot of the other core RTLIL methods
also are a bit too eager with unpacking or implementing
`SigChunk`/`Const` overloads that just convert to a single chunk
`SigSpec` and forward to the implementation for that, when a direct
implementation would avoid temporary std::vector allocations. While not
relevant for `read_rtlil`, to me it looks like there might be a few easy
overall performance gains to be had by addressing this more generally.
2024-04-22 13:26:17 +02:00
Jannis Harder d8687e87b1 kernel: Avoid including files outside include guards
This adjusts the way the headers kernel/{yosys,rtlil,register,log}.h
include each other to avoid the need of including headers outside of
include guards as well as avoiding the inclusion of rtlil.h in the
middle of yosys.h with rtlil.h depending on the prefix of yosys.h, and
the suffix of yosys.h depending on rtlil.h.

To do this I moved some of the declaration in yosys.h into a new header
yosys_common.h. I'm not sure if that is strictly necessary.

Including any of these files still results in the declarations of all
these headers being included, so this shouldn't be a breaking change for
any passes or external plugins.

My main motivation for this is that ccls's (clang based language server)
include guard handling gets confused by the previous way the includes
were done. It often ends up treating the include guard as a generic
disabled preprocessor conditional, breaking navigation and highlighting
for the core RTLIL data structures.

Additionally I think avoiding cyclic includes in the middle of header
files that depend on includes being outside of include guards will also
be less confusing for developers reading the code, not only for tools
like ccls.
2024-04-02 16:53:56 +02:00
Catherine 94170388a9 fmt: if enabled, group padding zeroes.
Before this commit, the combination of `_` and `0` format characters
would produce a result like `000000001010_1010`.
After this commit, it would be `0000_0000_1010_1010`.

This has a slight quirk where a format like `{:020_b}` results in
the output `0_0000_0000_1010_1010`, which is one character longer than
requested. Python has the same behavior, and it's not clear what would
be strictly speaking correct, so Python behavior is implemented.
2024-04-02 12:13:22 +02:00
Catherine 27cb4c52b4 fmt: allow padding characters other than '0' and ' '.
When converted to Verilog, padding characters are replaced with one of
these two. Otherwise padding is performed with exactly that character.
2024-04-02 12:13:22 +02:00
Catherine ddf7b46955 fmt,cxxrtl: fix printing of non-decimal signed numbers.
Also fix interaction of `NUMERIC` justification with `show_base`.
2024-04-02 12:13:22 +02:00
Catherine 00c5b60dfd fmt,cxxrtl: add option to group digits in numbers.
The option is serialized to RTLIL as `_` (to match Python's option with
the same symbol), and sets the `group` flag. This flag inserts an `_`
symbol between each group of 3 digits (for decimal) or four digits (for
binary, hex, and octal).
2024-04-02 12:13:22 +02:00
Catherine 7b94599162 fmt,cxxrtl: add option to print numeric base (0x, etc).
The option is serialized to RTLIL as `#` (to match Python's and Rust's
option with the same symbol), and sets the `show_base` flag. Because
the flag is called `show_base` and not e.g. `alternate_format` (which
is what Python and Rust call it), in addition to the prefixes `0x`,
`0X`, `0o`, `0b`, the RTLIL option also prints the `0d` prefix.
2024-04-02 12:13:22 +02:00
Catherine bf5a960668 fmt,cxxrtl: add UNICHAR format type.
This format type is used to print an Unicode character (code point) as
its UTF-8 serialization. To this end, two UTF-8 decoders (one for fmt,
one for cxxrtl) are added for rendering. When converted to a Verilog
format specifier, `UNICHAR` degrades to `%c` with the low 7 bits of
the code point, which has equivalent behavior for inputs not exceeding
ASCII. (SystemVerilog leaves source and display encodings completely
undefined.)
2024-04-02 12:13:22 +02:00
Catherine 1780e2eb1e fmt,cxxrtl: add support for NUMERIC justification.
Before this commit, the existing alignments were `LEFT` and `RIGHT`,
which added the `padding` character to the right and left just before
finishing formatting. However, if `padding == '0'` and the alignment is
to the right, then the padding character (digit zero) was added after
the sign, if one is present.

After this commit, the special case for `padding == '0'` is removed,
and the new justification `NUMERIC` adds the padding character like
the justification `RIGHT`, except after the sign, if one is present.
(Space, for the `SPACE_MINUS` sign mode, counts as the sign.)
2024-04-02 12:13:22 +02:00
Catherine 6d6b138607 fmt,cxxrtl: support {,PLUS_,SPACE_}MINUS integer formats.
The first two were already supported with the `plus` boolean flag.
The third one is a new specifier, which is allocated the ` ` character.
In addition, `MINUS` is now allocated the `-` character, but old format
where there is no `+`, `-`, or `-` in the respective position is also
accepted for compatibility.
2024-04-02 12:13:22 +02:00
Catherine 8388846e3a fmt,cxxrtl: add support for uppercase hex format.
This is necessary for translating Python format strings in Amaranth.
2024-04-02 12:13:22 +02:00
Catherine a5441bc00c fmt: FmtPart::{STRING→LITERAL},{CHARACTER→STRING}.
Before this commit, the `STRING` variant inserted a literal string;
the `CHARACTER` variant inserted a string. This commit renames them
to `LITERAL` and `STRING` respectively.
2024-04-02 12:13:22 +02:00
N. Engelhardt c98cdc2a42
Merge pull request #4184 from povik/check-loop-edges
Use cell edges data in `check`, improve messages
2024-03-25 16:19:35 +01:00
Krystine Sherwin 3eeefd23e3
Typo fixup(s) 2024-03-18 11:09:23 +13:00
Krystine Sherwin d2bf5a83af
Merge branch 'origin/master' into krys/docs 2024-03-18 10:39:30 +13:00
Miodrag Milanovic 5e05300e7b fix compile warning 2024-03-11 10:55:09 +01:00
Martin Povišer d01728aaa5 celledges: Register async FF paths 2024-03-11 10:45:36 +01:00
Martin Povišer 87e72ef86f celledges: Add read ports arst paths 2024-03-11 10:45:17 +01:00
Martin Povišer 4a10e78777 celledges: Emit empty edges for write/init ports 2024-03-11 10:45:17 +01:00
Martin Povišer 3a1ef44564 celledges: Describe asynchronous read ports 2024-03-11 10:45:17 +01:00
Martin Povišer 6e5f40e364 utils: Save detected loops with their nodes in-order 2024-03-11 10:43:49 +01:00
N. Engelhardt d70113a909
Merge pull request #3972 from nakengelhardt/celledges_shift_ops
celledges: support shift ops
2024-03-08 09:35:47 +01:00