tiny fix

kernel/ffmerge.cc

@@ -345,7 +345,7 @@ void FfMergeHelper::set(FfInitVals *initvals_, RTLIL::Module *module_)
 			for (int i = 0; i < GetSize(q); i++)
 				dff_driver[q[i]] = std::make_pair(cell, i);
 		}
-		for (auto &&conn : cell->connections_)
+		for (auto conn : cell->connections_)
 			if (!cell->known() || cell->input(conn.first))
 				for (auto bit : (*sigmap)(conn.second))
 					sigbit_users_count[bit]++;

kernel/rtlil.cc

@@ -1090,7 +1090,7 @@ namespace {
 			for (auto &&para : cell->parameters)
 				if (expected_params.count(para.first) == 0)
 					error(__LINE__);
-			for (auto &&conn : cell->connections_)
+			for (auto conn : cell->connections_)
 				if (expected_ports.count(conn.first) == 0)
 					error(__LINE__);
 

kernel/rtlil.h

@@ -1691,7 +1691,7 @@ public:
 			return parent->getParam(name);
 		}
 		void sort() {}
-		void reserve() {}
+		void reserve(int n) { (void)n; }
 		// Watch out! This is different semantics than what dict has!
 		// but we rely on RTLIL::Cell always being constructed correctly
 		// since its layout is fixed as defined by InternalOldCellChecker
@@ -1903,7 +1903,7 @@ public:
 			return parent->getPort(name);
 		}
 		void sort() {}
-		void reserve() {}
+		void reserve(int n) { (void)n; }
 		// Watch out! This is different semantics than what dict has!
 		// but we rely on RTLIL::Cell always being constructed correctly
 		// since its layout is fixed as defined by InternalOldCellChecker

passes/cmds/connwrappers.cc

@@ -105,7 +105,7 @@ struct ConnwrappersWorker
 
 		for (auto cell : module->selected_cells())
 		{
-			for (auto &&conn : cell->connections_)
+			for (auto conn : cell->connections_)
 			{
 				std::vector<RTLIL::SigBit> sigbits = sigmap(conn.second).to_sigbit_vector();
 				RTLIL::SigSpec old_sig;

passes/cmds/splice.cc

@@ -188,7 +188,7 @@ struct SpliceWorker
 		for (auto cell : mod_cells) {
 			if (!sel_by_wire && !design->selected(module, cell))
 				continue;
-			for (auto &&conn : cell->connections_)
+			for (auto conn : cell->connections_)
 				if (ct.cell_input(cell->type, conn.first)) {
 					if (ports.size() > 0 && !ports.count(conn.first))
 						continue;

passes/hierarchy/hierarchy.cc

@@ -575,7 +575,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 
 		RTLIL::Module *mod = design->module(cell->type);
 
-		for (auto &&conn : cell->connections_) {
+		for (auto conn : cell->connections_) {
 			int conn_size = conn.second.size();
 			RTLIL::IdString portname = conn.first;
 			if (portname.begins_with("$")) {

passes/opt/opt_clean.cc

@@ -361,7 +361,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
 	// gather the usage information for cells
 	for (auto &it : module->cells_) {
 		RTLIL::Cell *cell = it.second;
-		for (auto &it2 : cell->connections_) {
+		for (auto it2 : cell->connections_) {
 			assign_map.apply(it2.second); // modify the cell connection in place
 			raw_used_signals.add(it2.second);
 			used_signals.add(it2.second);

passes/sat/expose.cc

@@ -498,7 +498,7 @@ struct ExposePass : public Pass {
 				for (auto cell : module->cells()) {
 					if (!ct.cell_known(cell->type))
 						continue;
-					for (auto &&conn : cell->connections_)
+					for (auto conn : cell->connections_)
 						if (ct.cell_output(cell->type, conn.first))
 							conn.second = out_to_in_map(sigmap(conn.second));
 				}
@@ -519,7 +519,7 @@ struct ExposePass : public Pass {
 				for (auto cell : module->cells()) {
 					if (!ct.cell_known(cell->type))
 						continue;
-					for (auto &&conn : cell->connections_)
+					for (auto conn : cell->connections_)
 						if (ct.cell_input(cell->type, conn.first))
 							conn.second = out_to_in_map(sigmap(conn.second));
 				}