mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 01:25:33 +00:00
Code Activity

tiny fix

Browse source
This commit is contained in:
Emil J. Tywoniak 2024-06-13 21:37:22 +02:00
parent 866b7a7121
commit 4c9f68216a
8 changed files with 10 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

2
kernel/ffmerge.cc
View file

@ -345,7 +345,7 @@ void FfMergeHelper::set(FfInitVals *initvals_, RTLIL::Module *module_)
for (int i = 0; i < GetSize(q); i++)
dff_driver[q[i]] = std::make_pair(cell, i);
}
for (auto &&conn : cell->connections_)
for (auto conn : cell->connections_)
if (!cell->known() || cell->input(conn.first))
for (auto bit : (*sigmap)(conn.second))
sigbit_users_count[bit]++;

2
kernel/rtlil.cc
View file

@ -1090,7 +1090,7 @@ namespace {
for (auto &&para : cell->parameters)
if (expected_params.count(para.first) == 0)
error(__LINE__);
for (auto &&conn : cell->connections_)
for (auto conn : cell->connections_)
if (expected_ports.count(conn.first) == 0)
error(__LINE__);

4
kernel/rtlil.h
View file

@ -1691,7 +1691,7 @@ public:
return parent->getParam(name);
}
void sort() {}
void reserve() {}
void reserve(int n) { (void)n; }
// Watch out! This is different semantics than what dict has!
// but we rely on RTLIL::Cell always being constructed correctly
// since its layout is fixed as defined by InternalOldCellChecker
@ -1903,7 +1903,7 @@ public:
return parent->getPort(name);
}
void sort() {}
void reserve() {}
void reserve(int n) { (void)n; }
// Watch out! This is different semantics than what dict has!
// but we rely on RTLIL::Cell always being constructed correctly
// since its layout is fixed as defined by InternalOldCellChecker