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conns and params from dict, oldcell no longer attrobject

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This commit is contained in:
Emil J. Tywoniak 2024-06-13 21:34:42 +02:00
parent 193a43e82c
commit 866b7a7121
3 changed files with 49 additions and 8 deletions
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1
kernel/rtlil.cc
View file

@ -3750,7 +3750,6 @@ void RTLIL::OldCell::sort()
{
connections_.sort(sort_by_id_str());
parameters.sort(sort_by_id_str());
attributes.sort(sort_by_id_str());
}
void RTLIL::Cell::check()

53
kernel/rtlil.h
View file

@ -1552,7 +1552,7 @@ struct RTLIL::Memory : public RTLIL::AttrObject
};
struct RTLIL::OldCell : public RTLIL::AttrObject
struct RTLIL::OldCell
{
unsigned int hashidx_;
unsigned int hash() const { return hashidx_; }
@ -1597,10 +1597,10 @@ public:
// void check();
// void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);
bool has_keep_attr() const {
return get_bool_attribute(ID::keep) || (module && module->design && module->design->module(type) &&
module->design->module(type)->get_bool_attribute(ID::keep));
}
// bool has_keep_attr() const {
// return get_bool_attribute(ID::keep) || (module && module->design && module->design->module(type) &&
// module->design->module(type)->get_bool_attribute(ID::keep));
// }
template<typename T> void rewrite_sigspecs(T &functor);
template<typename T> void rewrite_sigspecs2(T &functor);
@ -1633,6 +1633,15 @@ struct RTLIL::Unary {
bool output(IdString portname) const {
return portname == ID::Y;
}
void conns_from_dict(dict<IdString, SigSpec> conns) {
a = conns[ID::A];
y = conns[ID::Y];
}
void params_from_dict(dict<IdString, Const> conns) {
a_width = conns[ID::A_WIDTH];
y_width = conns[ID::Y_WIDTH];
is_signed = conns[ID::A_SIGNED];
}
// TODO new interface: inputs
};
@ -1682,12 +1691,27 @@ public:
return parent->getParam(name);
}
void sort() {}
void reserve() {}
// Watch out! This is different semantics than what dict has!
// but we rely on RTLIL::Cell always being constructed correctly
// since its layout is fixed as defined by InternalOldCellChecker
RTLIL::Const& operator[](RTLIL::IdString name) {
return parent->getMutParam(name);
}
void operator=(dict<IdString, Const> from) {
if (parent->is_legacy())
parent->legacy->parameters = from;
if (parent->type == ID($not)) {
parent->not_.params_from_dict(from);
} else if (parent->type == ID($pos)) {
parent->pos.params_from_dict(from);
} else if (parent->type == ID($neg)) {
parent->neg.params_from_dict(from);
} else {
throw std::out_of_range("Cell::getParam()");
}
}
bool operator==(const FakeParams& other) const {
auto this_it = this->begin();
auto other_it = other.begin();
@ -1879,12 +1903,27 @@ public:
return parent->getPort(name);
}
void sort() {}
void reserve() {}
// Watch out! This is different semantics than what dict has!
// but we rely on RTLIL::Cell always being constructed correctly
// since its layout is fixed as defined by InternalOldCellChecker
RTLIL::SigSpec& operator[](RTLIL::IdString portname) {
return parent->getMutPort(portname);
}
void operator=(dict<IdString, SigSpec> from) {
if (parent->is_legacy())
parent->legacy->connections_ = from;
if (parent->type == ID($not)) {
parent->not_.conns_from_dict(from);
} else if (parent->type == ID($pos)) {
parent->pos.conns_from_dict(from);
} else if (parent->type == ID($neg)) {
parent->neg.conns_from_dict(from);
} else {
throw std::out_of_range("Cell::getParam()");
}
}
int count(RTLIL::IdString portname) const {
try {
parent->getPort(portname);
@ -2063,6 +2102,10 @@ public:
bool has_memid() { return is_legacy() && legacy->has_memid(); }
bool is_mem_cell() { return is_legacy() && legacy->is_mem_cell(); }
bool has_keep_attr() const {
return get_bool_attribute(ID::keep) || (module && module->design && module->design->module(type) &&
module->design->module(type)->get_bool_attribute(ID::keep));
}
// TODO stub
void set_src_attribute(const std::string &src) { (void)src; };
bool known () {

3
passes/fsm/fsm_extract.cc
View file

@ -395,8 +395,7 @@ static void extract_fsm(RTLIL::Wire *wire)
RTLIL::SigSpec port_sig = assign_map(cell->getPort(cellport.second));
RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%d", autoidx++), unconn_sig.size());
auto &x = cell->connections_[cellport.second];
port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), x);
port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), cell->connections_[cellport.second]);
}
}