mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-20 07:36:39 +00:00
Code Activity

erase, clear, fork replace, idk

Browse source
This commit is contained in:
Emil J. Tywoniak 2024-06-13 20:31:11 +02:00
parent cc10ef7019
commit 193a43e82c
13 changed files with 134 additions and 69 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
Makefile
View file

@ -566,6 +566,7 @@ $(eval $(call add_include_file,kernel/celledges.h))
$(eval $(call add_include_file,kernel/celltypes.h))
$(eval $(call add_include_file,kernel/consteval.h))
$(eval $(call add_include_file,kernel/constids.inc))
$(eval $(call add_include_file,kernel/compat.h))
$(eval $(call add_include_file,kernel/cost.h))
$(eval $(call add_include_file,kernel/ff.h))
$(eval $(call add_include_file,kernel/ffinit.h))
@ -606,7 +607,7 @@ $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h))
# See -DTRACY_ENABLE
OBJS += tracy/public/TracyClient.o
OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o
OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/compat.o
OBJS += kernel/binding.o
OBJS += kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o
ifeq ($(ENABLE_ZLIB),1)

2
backends/rtlil/rtlil_backend.cc
View file

@ -165,7 +165,7 @@ void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::
f << stringf("\n");
}
f << stringf("%s" "cell %s %s\n", indent.c_str(), cell->type.c_str(), cell->name.c_str());
for (auto &it : cell->parameters) {
for (auto &&it : cell->parameters) {
f << stringf("%s parameter%s%s %s ", indent.c_str(),
(it.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "",
(it.second.flags & RTLIL::CONST_FLAG_REAL) != 0 ? " real" : "",

6
kernel/compat.h
View file

@ -2,5 +2,11 @@
#ifndef COMPAT_H
#define COMPAT_H
YOSYS_NAMESPACE_BEGIN
dict<RTLIL::IdString, RTLIL::Const> cell_to_mod_params (const RTLIL::Cell::FakeParams& cell_params);
YOSYS_NAMESPACE_END
#endif

102
kernel/rtlil.cc
View file

@ -3525,9 +3525,9 @@ const RTLIL::SigSpec &RTLIL::Cell::getPort(const RTLIL::IdString &portname) cons
throw std::out_of_range("Cell::setPort()");
}
}
const RTLIL::SigSpec &RTLIL::Cell::getPort(const RTLIL::IdString &portname) {
RTLIL::SigSpec &RTLIL::Cell::getMutPort(const RTLIL::IdString &portname) {
if (is_legacy())
return legacy->getPort(portname);
return legacy->connections_[portname];
if (type == ID($not)) {
if (portname == ID::A) {
@ -3562,24 +3562,6 @@ void RTLIL::Cell::setParam(const RTLIL::IdString &paramname, RTLIL::Const value)
}
}
// // TODO autogen
// const RTLIL::Const RTLIL::Cell::getParam(const RTLIL::IdString &paramname) const {
// if (is_legacy())
// return legacy->getParam(paramname);
// if (type == ID($not)) {
// if (paramname == ID::A_WIDTH) {
// return RTLIL::Const(not_.a_width);
// } else if (paramname == ID::Y_WIDTH) {
// return RTLIL::Const(not_.y_width);
// } else {
// throw std::out_of_range("Cell::getParam()");
// }
// } else {
// throw std::out_of_range("Cell::getParam()");
// }
// }
const RTLIL::Const& RTLIL::Cell::getParam(const RTLIL::IdString &paramname) const {
if (is_legacy())
return legacy->getParam(paramname);
@ -3597,23 +3579,22 @@ const RTLIL::Const& RTLIL::Cell::getParam(const RTLIL::IdString &paramname) cons
}
}
// // Compatibility layer. Avoid using it
// inline RTLIL::Const &RTLIL::Cell::getParam(const RTLIL::IdString& paramname) const
// {
// if (is_legacy()) {
// return legacy->getParam(paramname);
// } else {
// // TODO auto-generate this
// if (type == ID($not)) {
// if (paramname == ID::A_WIDTH) {
// return RTLIL::Const(not_.a_width);
// // ...else if...
// } else {
// throw std::out_of_range("Cell::getParam()");
// }
// }
// }
// }
RTLIL::Const& RTLIL::Cell::getMutParam(const RTLIL::IdString &paramname) {
if (is_legacy())
return legacy->parameters[paramname];
if (type == ID($not)) {
if (paramname == ID::A_WIDTH) {
return not_.a_width;
} else if (paramname == ID::Y_WIDTH) {
return not_.y_width;
} else {
throw std::out_of_range("Cell::getParam()");
}
} else {
throw std::out_of_range("Cell::getParam()");
}
}
RTLIL::OldCell::OldCell() : module(nullptr)
{
@ -4256,11 +4237,58 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec
other->check();
}
void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec &other) const
{
log_assert(width_ == other.width_);
log_assert(pattern.width_ == with.width_);
pattern.unpack();
with.unpack();
unpack();
other.unpack();
dict<RTLIL::SigBit, int> pattern_to_with;
for (int i = 0; i < GetSize(pattern.bits_); i++) {
if (pattern.bits_[i].wire != NULL) {
pattern_to_with.emplace(pattern.bits_[i], i);
}
}
for (int j = 0; j < GetSize(bits_); j++) {
auto it = pattern_to_with.find(bits_[j]);
if (it != pattern_to_with.end()) {
other.bits_[j] = with.bits_[it->second];
}
}
other.check();
}
void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
{
replace(rules, this);
}
// TODO is this one even used?
void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec &other) const
{
cover("kernel.rtlil.sigspec.replace_dict");
log_assert(width_ == other.width_);
if (rules.empty()) return;
unpack();
other.unpack();
for (int i = 0; i < GetSize(bits_); i++) {
auto it = rules.find(bits_[i]);
if (it != rules.end())
other.bits_[i] = it->second;
}
other.check();
}
void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
{
cover("kernel.rtlil.sigspec.replace_dict");

57
kernel/rtlil.h
View file

@ -911,9 +911,11 @@ public:
void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);
void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const;
void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec &other) const;
void replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules);
void replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;
void replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec &other) const;
void replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules);
void replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const;
@ -1683,8 +1685,26 @@ public:
// Watch out! This is different semantics than what dict has!
// but we rely on RTLIL::Cell always being constructed correctly
// since its layout is fixed as defined by InternalOldCellChecker
RTLIL::Const operator[](RTLIL::IdString name) {
return parent->getParam(name);
RTLIL::Const& operator[](RTLIL::IdString name) {
return parent->getMutParam(name);
}
bool operator==(const FakeParams& other) const {
auto this_it = this->begin();
auto other_it = other.begin();
while (this_it != this->end() && other_it != other.end()) {
if (*this_it != *other_it)
return false;
++this_it;
++other_it;
}
if (this_it != this->end() || other_it != other.end()) {
// One has more params than the other
return false;
}
return true;
}
bool operator!=(const FakeParams& other) const {
return !operator==(other);
}
int count(RTLIL::IdString name) const {
try {
@ -1712,6 +1732,8 @@ public:
}
// The need for this function implies setPort will be used on incompat types
void erase(const RTLIL::IdString& paramname) { (void)paramname; }
// The need for this function implies setPort will be used on incompat types
void clear() {}
// AAA
class iterator {
typedef std::bidirectional_iterator_tag iterator_category;
@ -1747,7 +1769,7 @@ public:
} else if (parent->type == ID($not)) {
return parent->not_.parameters()[position];
} else {
throw std::out_of_range("FakeParams.iterator::operator*()");
throw std::out_of_range("FakeParams::iterator::operator*()");
}
}
// std::pair<IdString, Const&> operator->() { return operator*(); }
@ -1766,7 +1788,7 @@ public:
} else if (parent->type == ID($not)) {
return parent->not_.parameters()[position];
} else {
throw std::out_of_range("FakeParams.iterator::operator*() const");
throw std::out_of_range("FakeParams::iterator::operator*() const");
}
}
};
@ -1789,7 +1811,7 @@ public:
} else if (parent->type == ID($not)) {
return iterator(parent, parent->not_.connections().size());
} else {
throw std::out_of_range("FakeParams.iterator::end()");
throw std::out_of_range("FakeParams::iterator::end()");
}
}
// AAA CONST ITERATOR
@ -1827,7 +1849,7 @@ public:
} else if (parent->type == ID($not)) {
return parent->not_.parameters()[position];
} else {
throw std::out_of_range("FakeConns.const_iterator::operator*() const");
throw std::out_of_range("FakeParams::const_iterator::operator*() const");
}
}
};
@ -1860,10 +1882,10 @@ public:
// Watch out! This is different semantics than what dict has!
// but we rely on RTLIL::Cell always being constructed correctly
// since its layout is fixed as defined by InternalOldCellChecker
RTLIL::SigSpec operator[](RTLIL::IdString portname) {
return parent->getPort(portname);
RTLIL::SigSpec& operator[](RTLIL::IdString portname) {
return parent->getMutPort(portname);
}
int count(RTLIL::IdString portname) {
int count(RTLIL::IdString portname) const {
try {
parent->getPort(portname);
} catch (const std::out_of_range& e) {
@ -1884,6 +1906,10 @@ public:
throw std::out_of_range("FakeConns::size()");
}
}
// The need for this function implies setPort will be used on incompat types
void erase(const RTLIL::IdString& portname) { (void)portname; }
// The need for this function implies setPort will be used on incompat types
void clear() {}
bool empty() {
return !size();
}
@ -1923,7 +1949,7 @@ public:
} else if (parent->type == ID($not)) {
return parent->not_.connections()[position];
} else {
throw std::out_of_range("FakeConns.iterator::operator*()");
throw std::out_of_range("FakeConns::iterator::operator*()");
}
}
// std::pair<IdString, SigSpec&> operator->() { return operator*(); }
@ -1943,7 +1969,7 @@ public:
} else if (parent->type == ID($not)) {
return parent->not_.connections()[position];
} else {
throw std::out_of_range("FakeConns.iterator::operator*() const");
throw std::out_of_range("FakeConns::iterator::operator*() const");
}
}
};
@ -1966,7 +1992,7 @@ public:
} else if (parent->type == ID($not)) {
return iterator(parent, parent->not_.connections().size());
} else {
throw std::out_of_range("FakeConns.iterator::end()");
throw std::out_of_range("FakeConns::iterator::end()");
}
}
// AAA CONST ITERATOR
@ -2004,7 +2030,7 @@ public:
} else if (parent->type == ID($not)) {
return parent->not_.connections()[position];
} else {
throw std::out_of_range("FakeConns.const_iterator::operator*() const");
throw std::out_of_range("FakeConns::const_iterator::operator*() const");
}
}
};
@ -2072,7 +2098,7 @@ public:
void setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal);
// TODO is this reasonable at all?
const RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const;
const RTLIL::SigSpec &getPort(const RTLIL::IdString &portname);
RTLIL::SigSpec &getMutPort(const RTLIL::IdString &portname);
bool hasPort(const RTLIL::IdString &portname) {
return connections_.count(portname);
}
@ -2081,8 +2107,7 @@ public:
void setParam(const RTLIL::IdString &paramname, RTLIL::Const value);
// TODO is this reasonable at all?
const RTLIL::Const& getParam(const RTLIL::IdString &paramname) const;
// const RTLIL::Const& getParam(const RTLIL::IdString &paramname);
RTLIL::Const& getParam(const RTLIL::IdString &paramname);
RTLIL::Const& getMutParam(const RTLIL::IdString &paramname);
bool hasParam(const RTLIL::IdString &paramname) {
return parameters.count(paramname);
}

3
passes/cmds/sta.cc
View file

@ -21,6 +21,7 @@
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
#include "kernel/timinginfo.h"
#include "kernel/compat.h"
#include <deque>
USING_YOSYS_NAMESPACE
@ -74,7 +75,7 @@ struct StaWorker
continue;
}
IdString derived_type = inst_module->derive(design, cell->parameters);
IdString derived_type = inst_module->derive(design, cell_to_mod_params(cell->parameters));
inst_module = design->module(derived_type);
log_assert(inst_module);

2
passes/equiv/equiv_struct.cc
View file

@ -162,7 +162,7 @@ struct EquivStructWorker
Cell *cell = module->cell(cell_name);
key.type = cell->type;
for (auto &it : cell->parameters)
for (auto &&it : cell->parameters)
key.parameters.push_back(it);
std::sort(key.parameters.begin(), key.parameters.end());

3
passes/fsm/fsm_extract.cc
View file

@ -395,7 +395,8 @@ static void extract_fsm(RTLIL::Wire *wire)
RTLIL::SigSpec port_sig = assign_map(cell->getPort(cellport.second));
RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%d", autoidx++), unconn_sig.size());
port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]);
auto &x = cell->connections_[cellport.second];
port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), x);
}
}

3
passes/fsm/fsmdata.h
View file

@ -48,7 +48,8 @@ struct FsmData
cell->parameters[ID::STATE_TABLE] = RTLIL::Const();
for (int i = 0; i < int(state_table.size()); i++) {
std::vector<RTLIL::State> &bits_table = cell->parameters[ID::STATE_TABLE].bits;
auto thing = cell->parameters[ID::STATE_TABLE];
std::vector<RTLIL::State> &bits_table = thing.bits;
std::vector<RTLIL::State> &bits_state = state_table[i].bits;
bits_table.insert(bits_table.end(), bits_state.begin(), bits_state.end());
}

13
passes/hierarchy/hierarchy.cc
View file

@ -19,6 +19,7 @@
*/
#include "kernel/yosys.h"
#include "kernel/compat.h"
#include "frontends/verific/verific.h"
#include <stdlib.h>
#include <stdio.h>
@ -69,7 +70,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
portnames.insert(conn.first);
portwidths[conn.first] = max(portwidths[conn.first], conn.second.size());
}
for (auto &para : cell->parameters)
for (auto &&para : cell->parameters)
parameters.insert(para.first);
}
@ -334,7 +335,7 @@ RTLIL::Module *get_module(RTLIL::Design &design,
std::string cell_type = cell.type.str();
RTLIL::Module *abs_mod = design.module("$abstract" + cell_type);
if (abs_mod) {
cell.type = abs_mod->derive(&design, cell.parameters);
cell.type = abs_mod->derive(&design, cell_to_mod_params(cell.parameters));
cell.parameters.clear();
RTLIL::Module *mod = design.module(cell.type);
log_assert(mod);
@ -418,7 +419,7 @@ void check_cell_connections(const RTLIL::Module &module, RTLIL::Cell &cell, RTLI
log_id(conn.first));
}
}
for (auto &param : cell.parameters) {
for (auto param : cell.parameters) {
if (read_id_num(param.first, &id)) {
if (id <= 0 || id > GetSize(mod.avail_parameters))
log_error("Module `%s' referenced in module `%s' in cell `%s' "
@ -528,7 +529,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
}
cell->type = mod->derive(design,
cell->parameters,
cell_to_mod_params(cell->parameters),
if_expander.interfaces_to_add_to_submodule,
if_expander.modports_used_in_submodule);
cell->parameters.clear();
@ -1237,7 +1238,7 @@ struct HierarchyPass : public Pass {
// Need accurate port widths for error checking; so must derive blackboxes with dynamic port widths
if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute(ID::dynports)) {
IdString new_m_name = m->derive(design, cell->parameters, true);
IdString new_m_name = m->derive(design, cell_to_mod_params(cell->parameters), true);
if (new_m_name.empty())
continue;
if (new_m_name != m->name) {
@ -1420,7 +1421,7 @@ struct HierarchyPass : public Pass {
continue;
if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute(ID::dynports)) {
IdString new_m_name = m->derive(design, cell->parameters, true);
IdString new_m_name = m->derive(design, cell_to_mod_params(cell->parameters), true);
if (new_m_name.empty())
continue;
if (new_m_name != m->name) {

2
passes/hierarchy/submod.cc
View file

@ -208,7 +208,7 @@ struct SubmodWorker
for (RTLIL::Cell *cell : submod.cells) {
RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell);
for (auto &conn : new_cell->connections_)
for (auto conn : new_cell->connections_)
for (auto &bit : conn.second)
if (bit.wire != nullptr) {
log_assert(wire_flags.count(bit.wire) > 0);

2
passes/opt/opt_merge.cc
View file

@ -140,7 +140,7 @@ struct OptMergeWorker
hash_conn_strings.push_back(s + "\n");
}
for (auto &it : cell->parameters)
for (auto &&it : cell->parameters)
hash_conn_strings.push_back("P " + it.first.str() + "=" + it.second.as_string() + "\n");
std::sort(hash_conn_strings.begin(), hash_conn_strings.end());

5
passes/techmap/abc9_ops.cc
View file

@ -23,6 +23,7 @@
#include "kernel/utils.h"
#include "kernel/celltypes.h"
#include "kernel/timinginfo.h"
#include "kernel/compat.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@ -113,7 +114,7 @@ void check(RTLIL::Design *design, bool dff_mode)
// but not its existence)
if (!inst_module->has_attribute(ID::abc9_flop))
continue;
derived_type = inst_module->derive(design, cell->parameters);
derived_type = inst_module->derive(design, cell_to_mod_params(cell->parameters));
derived_module = design->module(derived_type);
log_assert(derived_module);
}
@ -170,7 +171,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
derived_module = inst_module;
}
else {
derived_type = inst_module->derive(design, cell->parameters);
derived_type = inst_module->derive(design, cell_to_mod_params(cell->parameters));
derived_module = design->module(derived_type);
unused_derived.insert(derived_type);
}