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fix stuff, don't strip

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This commit is contained in:
Emil J. Tywoniak 2024-06-05 22:21:31 +02:00
parent 60bf00ea79
commit b85062fcec
2 changed files with 2 additions and 9 deletions
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3
flake.nix
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@ -24,12 +24,13 @@
preConfigure = "make config-clang";
checkTarget = "test";
installPhase = ''
make install PREFIX=$out ABCEXTERNAL=yosys-abc
make install PREFIX=$out ABCEXTERNAL=yosys-abc STRIP=\#
ln -s ${abc-verifier}/bin/abc $out/bin/yosys-abc
'';
buildPhase = ''
make -j$(nproc) ABCEXTERNAL=yosys-abc
'';
dontStrip = true;
meta = with pkgs.lib; {
description = "Yosys Open SYnthesis Suite";
homepage = "https://yosyshq.net/yosys/";

8
kernel/rtlil.cc
View file

@ -928,7 +928,6 @@ RTLIL::Module::Module()
design = nullptr;
refcount_wires_ = 0;
refcount_cells_ = 0;
TracyAllocN(this, sizeof(RTLIL::Module), "module");
#ifdef WITH_PYTHON
RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
@ -947,7 +946,6 @@ RTLIL::Module::~Module()
delete pr.second;
for (auto binding : bindings_)
delete binding;
TracyFree(this);
#ifdef WITH_PYTHON
RTLIL::Module::get_all_modules()->erase(hashidx_);
#endif
@ -3460,17 +3458,11 @@ RTLIL::Memory::Memory()
#endif
}
RTLIL::Process::~Process()
{
TracyFree(this);
}
RTLIL::Process::Process() : module(nullptr)
{
static unsigned int hashidx_count = 123456789;
hashidx_count = mkhash_xorshift(hashidx_count);
hashidx_ = hashidx_count;
TracyAllocN(this, sizeof(RTLIL::Process), "process");
}
RTLIL::Cell::Cell() : module(nullptr)