look at all those chickens

backends/intersynth/intersynth.cc

@@ -175,7 +175,7 @@ struct IntersynthBackend : public Backend {
 						node_code += stringf(" %s %s", log_id(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str());
 					}
 				}
-				for (auto &param : cell->parameters) {
+				for (auto &&param : cell->parameters) {
 					celltype_code += stringf(" cfg:%d %s", int(param.second.bits.size()), log_id(param.first));
 					if (param.second.bits.size() != 32) {
 						node_code += stringf(" %s '", log_id(param.first));

frontends/aiger/aigerparse.cc

@@ -766,7 +766,8 @@ void AigerReader::post_process()
 {
 	unsigned ci_count = 0, co_count = 0;
 	for (auto cell : boxes) {
-		for (auto &bit : cell->connections_.at(ID(i))) {
+		auto sig_inp = cell->connections_.at(ID(i));
+		for (auto &bit : sig_inp) {
 			log_assert(bit == State::S0);
 			log_assert(co_count < outputs.size());
 			bit = outputs[co_count++];
@@ -774,7 +775,8 @@ void AigerReader::post_process()
 			log_assert(bit.wire->port_output);
 			bit.wire->port_output = false;
 		}
-		for (auto &bit : cell->connections_.at(ID(o))) {
+		auto sig_outp = cell->connections_.at(ID(i));
+		for (auto &bit : sig_outp) {
 			log_assert(bit == State::S0);
 			log_assert((piNum + ci_count) < inputs.size());
 			bit = inputs[piNum + ci_count++];

frontends/blif/blifparse.cc

@@ -125,7 +125,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 	};
 
 	dict<RTLIL::IdString, RTLIL::Const> *obj_attributes = nullptr;
-	dict<RTLIL::IdString, RTLIL::Const> *obj_parameters = nullptr;
+	RTLIL::Cell::FakeParams *obj_parameters = nullptr;
 
 	dict<RTLIL::IdString, std::pair<int, bool>> wideports_cache;
 

frontends/json/jsonparse.cc

@@ -274,7 +274,8 @@ Const json_parse_attr_param_value(JsonNode *node)
 	return value;
 }
 
-void json_parse_attr_param(dict<IdString, Const> &results, JsonNode *node)
+template <typename SmellsLikeDict>
+void json_parse_attr_param(SmellsLikeDict &results, JsonNode *node)
 {
 	if (node->type != 'D')
 		log_error("JSON attributes or parameters node is not a dictionary.\n");

kernel/rtlil.cc

@@ -3580,22 +3580,6 @@ void RTLIL::Cell::setParam(const RTLIL::IdString &paramname, RTLIL::Const value)
 // 	}
 // }
 
-const RTLIL::Const& RTLIL::Cell::getParam(const RTLIL::IdString &paramname) {
-	if (is_legacy())
-		return legacy->getParam(paramname);
-
-	if (type == ID($not)) {
-		if (paramname == ID::A_WIDTH) {
-			return not_.a_width;
-		} else if (paramname == ID::Y_WIDTH) {
-			return not_.y_width;
-		} else {
-			throw std::out_of_range("Cell::getParam()");
-		}
-	} else {
-		throw std::out_of_range("Cell::getParam()");
-	}
-}
 const RTLIL::Const& RTLIL::Cell::getParam(const RTLIL::IdString &paramname) const {
 	if (is_legacy())
 		return legacy->getParam(paramname);

kernel/rtlil.h

@@ -1625,10 +1625,10 @@ struct RTLIL::Unary {
 	std::array<std::pair<IdString, Const&>, 3> parameters() {
 		return {std::make_pair(ID::A_WIDTH, std::ref(a_width)), std::make_pair(ID::Y_WIDTH, std::ref(y_width)), std::make_pair(ID::A_SIGNED, std::ref(y_width))};
 	}
-	bool input(IdString portname) {
+	bool input(IdString portname) const {
 		return portname == ID::A;
 	}
-	bool output(IdString portname) {
+	bool output(IdString portname) const {
 		return portname == ID::Y;
 	}
 	// TODO new interface: inputs
@@ -1660,9 +1660,22 @@ public:
 	};
 	struct FakeParams {
 		RTLIL::Cell* parent;
-		// RTLIL::Const& at(RTLIL::IdString name) {
-		// 	return parent->getParam(name);
-		// }
+		RTLIL::Const& at(RTLIL::IdString paramname) {
+			if (parent->is_legacy())
+				return parent->legacy->parameters.at(paramname);
+
+			if (parent->type == ID($not)) {
+				if (paramname == ID::A_WIDTH) {
+					return parent->not_.a_width;
+				} else if (paramname == ID::Y_WIDTH) {
+					return parent->not_.y_width;
+				} else {
+					throw std::out_of_range("Cell::getParam()");
+				}
+			} else {
+				throw std::out_of_range("Cell::getParam()");
+			}
+		}
 		const RTLIL::Const& at(RTLIL::IdString name) const {
 			return parent->getParam(name);
 		}
@@ -1673,7 +1686,7 @@ public:
 		RTLIL::Const operator[](RTLIL::IdString name) {
 			return parent->getParam(name);
 		}
-		int count(RTLIL::IdString name) {
+		int count(RTLIL::IdString name) const {
 			try {
 				parent->getParam(name);
 			} catch (const std::out_of_range& e) {
@@ -2029,7 +2042,7 @@ public:
 	bool known () {
 		return is_legacy() ? legacy->known() : true;
 	}
-	bool input(const RTLIL::IdString &portname) {
+	bool input(const RTLIL::IdString &portname) const {
 		if (is_legacy()) {
 			return legacy->input(portname);
 		} else if (type == ID($pos)) {
@@ -2042,7 +2055,7 @@ public:
 			throw std::out_of_range("FakeParams::size()");
 		}
 	}
-	bool output(const RTLIL::IdString &portname) {
+	bool output(const RTLIL::IdString &portname) const {
 		if (is_legacy()) {
 			return legacy->output(portname);
 		} else if (type == ID($pos)) {
@@ -2068,10 +2081,13 @@ public:
 	void setParam(const RTLIL::IdString &paramname, RTLIL::Const value);
 	// TODO is this reasonable at all?
 	const RTLIL::Const& getParam(const RTLIL::IdString &paramname) const;
-	const RTLIL::Const& getParam(const RTLIL::IdString &paramname);
+	// const RTLIL::Const& getParam(const RTLIL::IdString &paramname);
+	RTLIL::Const& getParam(const RTLIL::IdString &paramname);
 	bool hasParam(const RTLIL::IdString &paramname) {
 		return parameters.count(paramname);
 	}
+	// The need for this function implies setPort will be used on incompat types
+	void unsetParam(const RTLIL::IdString& paramname) { (void)paramname; }
 	template<typename T>
 	void rewrite_sigspecs2(T &functor) {
 		// for(auto it = connections_.begin(); it != connections_.end(); ++it) {

passes/cmds/connect.cc

@@ -33,7 +33,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
 	RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size());
 
 	for (auto cell : module->cells())
-	for (auto &port : cell->connections_)
+	for (auto &&port : cell->connections_)
 		if (ct.cell_output(cell->type, port.first))
 			sigmap(port.second).replace(sig, dummy_wire, &port.second);
 

passes/cmds/connwrappers.cc

@@ -105,7 +105,7 @@ struct ConnwrappersWorker
 
 		for (auto cell : module->selected_cells())
 		{
-			for (auto &conn : cell->connections_)
+			for (auto &&conn : cell->connections_)
 			{
 				std::vector<RTLIL::SigBit> sigbits = sigmap(conn.second).to_sigbit_vector();
 				RTLIL::SigSpec old_sig;

passes/cmds/glift.cc

@@ -343,9 +343,9 @@ private:
 				//recurse to GLIFT model the child module. However, we need to augment the ports list
 				//with taint signals and connect the new ports to the corresponding taint signals.
 				RTLIL::Module *cell_module_def = module->design->module(cell->type);
-				dict<RTLIL::IdString, RTLIL::SigSpec> orig_ports = cell->connections();
+				auto orig_ports = cell->connections();
 				log("Adding cell %s\n", cell_module_def->name.c_str());
-				for (auto &it : orig_ports) {
+				for (auto &&it : orig_ports) {
 					RTLIL::SigSpec port = it.second;
 					RTLIL::SigSpec port_taint = get_corresponding_taint_signal(port);
 

passes/cmds/select.cc

@@ -106,7 +106,8 @@ static bool match_attr_val(const RTLIL::Const &value, const std::string &pattern
 	log_abort();
 }
 
-static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, const std::string &name_pat, const std::string &value_pat, char match_op)
+template <typename SmellsLikeDict>
+static bool match_attr(const SmellsLikeDict &attributes, const std::string &name_pat, const std::string &value_pat, char match_op)
 {
 	if (name_pat.find('*') != std::string::npos || name_pat.find('?') != std::string::npos || name_pat.find('[') != std::string::npos) {
 		for (auto &it : attributes) {
@@ -124,7 +125,8 @@ static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, co
 	return false;
 }
 
-static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, const std::string &match_expr)
+template <typename SmellsLikeDict>
+static bool match_attr(const SmellsLikeDict &attributes, const std::string &match_expr)
 {
 	size_t pos = match_expr.find_first_of("<!=>");
 

passes/cmds/setattr.cc

@@ -45,7 +45,8 @@ struct setunset_t
 	}
 };
 
-static void do_setunset(dict<RTLIL::IdString, RTLIL::Const> &attrs, const std::vector<setunset_t> &list)
+template <typename SmellsLikeDict>
+static void do_setunset(SmellsLikeDict &attrs, const std::vector<setunset_t> &list)
 {
 	for (auto &item : list)
 		if (item.unset)

passes/cmds/setundef.cc

@@ -245,7 +245,7 @@ struct SetundefPass : public Pass {
 			if (params_mode)
 			{
 				for (auto *cell : module->selected_cells()) {
-					for (auto &parameter : cell->parameters) {
+					for (auto &&parameter : cell->parameters) {
 						for (auto &bit : parameter.second.bits) {
 							if (bit > RTLIL::State::S1)
 								bit = worker.next_bit();

passes/cmds/splice.cc

@@ -188,7 +188,7 @@ struct SpliceWorker
 		for (auto cell : mod_cells) {
 			if (!sel_by_wire && !design->selected(module, cell))
 				continue;
-			for (auto &conn : cell->connections_)
+			for (auto &&conn : cell->connections_)
 				if (ct.cell_input(cell->type, conn.first)) {
 					if (ports.size() > 0 && !ports.count(conn.first))
 						continue;

passes/hierarchy/hierarchy.cc

@@ -574,7 +574,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 
 		RTLIL::Module *mod = design->module(cell->type);
 
-		for (auto &conn : cell->connections_) {
+		for (auto &&conn : cell->connections_) {
 			int conn_size = conn.second.size();
 			RTLIL::IdString portname = conn.first;
 			if (portname.begins_with("$")) {

passes/sat/expose.cc

@@ -498,7 +498,7 @@ struct ExposePass : public Pass {
 				for (auto cell : module->cells()) {
 					if (!ct.cell_known(cell->type))
 						continue;
-					for (auto &conn : cell->connections_)
+					for (auto &&conn : cell->connections_)
 						if (ct.cell_output(cell->type, conn.first))
 							conn.second = out_to_in_map(sigmap(conn.second));
 				}
@@ -519,7 +519,7 @@ struct ExposePass : public Pass {
 				for (auto cell : module->cells()) {
 					if (!ct.cell_known(cell->type))
 						continue;
-					for (auto &conn : cell->connections_)
+					for (auto &&conn : cell->connections_)
 						if (ct.cell_input(cell->type, conn.first))
 							conn.second = out_to_in_map(sigmap(conn.second));
 				}