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This commit is contained in:
Emil J. Tywoniak 2024-06-13 22:50:21 +02:00
parent 4c9f68216a
commit eeb15ea2a2
17 changed files with 121 additions and 38 deletions
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12
kernel/rtlil.cc
View file

@ -1087,7 +1087,7 @@ namespace {
void check_expected(bool check_matched_sign = false)
{
for (auto &&para : cell->parameters)
for (auto para : cell->parameters)
if (expected_params.count(para.first) == 0)
error(__LINE__);
for (auto conn : cell->connections_)
@ -1973,14 +1973,14 @@ void RTLIL::Module::check()
log_assert(it.first == it.second->name);
log_assert(!it.first.empty());
log_assert(!it.second->type.empty());
for (auto &&it2 : it.second->connections_) {
for (auto it2 : it.second->connections_) {
log_assert(!it2.first.empty());
it2.second.check(this);
}
// TODO
// for (auto &&it2 : it.second->attributes)
// log_assert(!it2.first.empty());
for (auto &&it2 : it.second->parameters)
for (auto it2 : it.second->parameters)
log_assert(!it2.first.empty());
InternalOldCellChecker checker(this, it.second);
checker.check();
@ -2493,9 +2493,9 @@ RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name, const RTLIL::Pro
add ## _func(name, sig_a, sig_y, is_signed, src); \
return sig_y; \
}
DEF_METHOD(Not, sig_a.size(), ID($not))
DEF_METHOD(Pos, sig_a.size(), ID($pos))
DEF_METHOD(Neg, sig_a.size(), ID($neg))
// DEF_METHOD(Not, sig_a.size(), ID($not))
// DEF_METHOD(Pos, sig_a.size(), ID($pos))
// DEF_METHOD(Neg, sig_a.size(), ID($neg))
DEF_METHOD(ReduceAnd, 1, ID($reduce_and))
DEF_METHOD(ReduceOr, 1, ID($reduce_or))
DEF_METHOD(ReduceXor, 1, ID($reduce_xor))

88
kernel/rtlil.h
View file

@ -1690,6 +1690,31 @@ public:
const RTLIL::Const& at(RTLIL::IdString name) const {
return parent->getParam(name);
}
const RTLIL::Const& at(RTLIL::IdString name, const RTLIL::Const& def) const {
if (parent->hasParam(name))
return parent->getParam(name);
else
return def;
}
dict<IdString, Const> as_dict() const {
if (parent->is_legacy())
return parent->legacy->parameters;
auto d = dict<IdString, Const>();
if (parent->type == ID($not)) {
for (auto conn: parent->not_.parameters())
d[conn.first] = conn.second;
} else if (parent->type == ID($pos)) {
for (auto conn: parent->pos.parameters())
d[conn.first] = conn.second;
} else if (parent->type == ID($neg)) {
for (auto conn: parent->neg.parameters())
d[conn.first] = conn.second;
} else {
throw std::out_of_range("Cell::getParam()");
}
return d;
}
void sort() {}
void reserve(int n) { (void)n; }
// Watch out! This is different semantics than what dict has!
@ -1880,6 +1905,11 @@ public:
const_iterator begin() const {
return const_iterator(parent, 0);
}
const_iterator find(const IdString name) const {
auto it = const_iterator(parent, 0);
for (; it != end() && (*it).first != name; ++it) {}
return it;
}
const_iterator end() const {
if (parent->is_legacy()) {
return const_iterator(parent, parent->legacy->connections_.size());
@ -1896,12 +1926,37 @@ public:
};
struct FakeConns {
RTLIL::Cell* parent;
// RTLIL::SigSpec at(RTLIL::IdString name) {
// return parent->getPort(name);
// }
RTLIL::SigSpec at(RTLIL::IdString name) {
return parent->getMutPort(name);
}
const RTLIL::SigSpec& at(RTLIL::IdString name) const {
return parent->getPort(name);
}
const RTLIL::SigSpec& at(RTLIL::IdString name, const RTLIL::SigSpec& def) const {
if (parent->hasPort(name))
return parent->getPort(name);
else
return def;
}
dict<IdString, SigSpec> as_dict() const {
if (parent->is_legacy())
return parent->legacy->connections_;
auto d = dict<IdString, SigSpec>();
if (parent->type == ID($not)) {
for (auto conn: parent->not_.connections())
d[conn.first] = conn.second;
} else if (parent->type == ID($pos)) {
for (auto conn: parent->pos.connections())
d[conn.first] = conn.second;
} else if (parent->type == ID($neg)) {
for (auto conn: parent->neg.connections())
d[conn.first] = conn.second;
} else {
throw std::out_of_range("Cell::getParam()");
}
return d;
}
void sort() {}
void reserve(int n) { (void)n; }
// Watch out! This is different semantics than what dict has!
@ -1924,6 +1979,24 @@ public:
throw std::out_of_range("Cell::getParam()");
}
}
bool operator==(const FakeConns& other) const {
auto this_it = this->begin();
auto other_it = other.begin();
while (this_it != this->end() && other_it != other.end()) {
if (*this_it != *other_it)
return false;
++this_it;
++other_it;
}
if (this_it != this->end() || other_it != other.end()) {
// One has more params than the other
return false;
}
return true;
}
bool operator!=(const FakeConns& other) const {
return !operator==(other);
}
int count(RTLIL::IdString portname) const {
try {
parent->getPort(portname);
@ -2076,6 +2149,11 @@ public:
const_iterator begin() const {
return const_iterator(parent, 0);
}
const_iterator find(const IdString name) const {
auto it = const_iterator(parent, 0);
for (; it != end() && (*it).first != name; ++it) {}
return it;
}
const_iterator end() const {
if (parent->is_legacy()) {
return const_iterator(parent, parent->legacy->connections_.size());
@ -2163,12 +2241,12 @@ public:
// functor(it.second);
// }
// TODO fix!!!
for (auto &&it : connections_)
for (auto it : connections_)
functor(it.second);
}
template<typename T>
void rewrite_sigspecs(T &functor) {
for (auto &&it : connections_)
for (auto it : connections_)
functor(it.second);
}
void sort() {