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Author SHA1 Message Date
Eddie Hung fd72c1c995 techlibs/common/simlib.v: EN_{SRC,DST} -> {SRC,DST}_EN 2020-05-05 08:30:36 -07:00
Eddie Hung 5a33f089bf Cleanup 2020-05-05 07:51:22 -07:00
Eddie Hung 6b403d19c7 More generic arch/xilinx/fsm test 2020-05-05 07:51:22 -07:00
Eddie Hung e6642d2928 sta: assume input-less modules to be constant drivers and don't warn ... 
if no timing arcs. Also handle undefined modules with a warning
 2020-05-05 07:51:22 -07:00
Eddie Hung 9cf172b7a9 sta: better handling when no timing paths and unused bits 2020-05-05 07:51:22 -07:00
Eddie Hung 10eaeabe1e sta: use ID::sta_arrival 2020-05-05 07:51:22 -07:00
Eddie Hung cf6b60f79c sta: more graceful when maxbit is not an endpoint, will still print path 2020-05-05 07:51:22 -07:00
Eddie Hung 72d73fe4d0 sta: missing sigmap 2020-05-05 07:51:22 -07:00
Eddie Hung d58a648f45 sta: do not consider constant bits 2020-05-05 07:51:22 -07:00
Eddie Hung c5e13f412a sta: do not add constant driven POs as endpoints 2020-05-05 07:51:22 -07:00
Eddie Hung 2561121b22 sta: ignore timing arc if no input port 2020-05-05 07:51:22 -07:00
Eddie Hung a921985e3c ice40: remove `ifdef TIMING for SB_IO & SB_GB, add specify for SB_GB_IO 2020-05-05 07:51:22 -07:00
Eddie Hung 70e198f9f9 sta: tune output 2020-05-05 07:51:22 -07:00
Eddie Hung e4aaebf2c9 abc9: use "source -x" for script files 2020-05-05 07:51:22 -07:00
Eddie Hung d523168a1c sta: track and print source port too 2020-05-05 07:51:22 -07:00
Eddie Hung 5084fa9d8a Revert "verilog: specify polarity to be separate token" 
This reverts commit 2122e0d053de659d5264500dc18965ba10013590.
 2020-05-05 07:51:22 -07:00
Eddie Hung ddbe81df78 timinginfo: arrival/required times with clocks 2020-05-05 07:51:22 -07:00
Eddie Hung b96866c456 Uncomment negative setup times; clamp to zero for connectivity 2020-05-05 07:51:22 -07:00
Eddie Hung 9c640bfdd2 sta: reverse LHS of histogram 2020-05-05 07:51:22 -07:00
Eddie Hung f157f6cba3 sta: print out arrival histogram 2020-05-05 07:51:22 -07:00
Eddie Hung dedaab3a7d sta: proof of concept to compute arrival times 2020-05-05 07:51:22 -07:00
Eddie Hung c6b22f5b7d verilog: specify polarity to be separate token 2020-05-05 07:51:22 -07:00
whitequark ae409d4d81
Merge pull request #2012 from whitequark/fix-wasi-abc-build 
Fix WASI builds with abc enabled
 2020-05-05 14:03:40 +00:00
Eddie Hung 5fa06e4894
Merge pull request #2026 from YosysHQ/eddie/scratchpad_abc9_W 
synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad
 2020-05-05 06:49:36 -07:00
Eddie Hung 7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src 
verilog: set src attribute for primitives
 2020-05-05 06:49:18 -07:00
Eddie Hung 99aff5a0f9
Merge pull request #2023 from YosysHQ/eddie/specify_src 
verilog: fix specify src attribute
 2020-05-05 06:49:06 -07:00
Eddie Hung e6b55e8b38 synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad 2020-05-04 11:44:00 -07:00
Eddie Hung eb5eb60fd4 verilog: fix specify src attribute 2020-05-04 10:53:06 -07:00
Eddie Hung eca9fc01a7 verilog: set src attribute for primitives 2020-05-04 10:22:05 -07:00
Eddie Hung ad8e7878f6 tests: add tests for primitives' src 2020-05-04 10:21:47 -07:00
Eddie Hung 584780d776
Merge pull request #1996 from boqwxp/rtlil_source_locations 
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
 2020-05-04 08:58:50 -07:00
whitequark d1c8837572
Merge pull request #2000 from whitequark/log_error-trap 
kernel: Trap in `log_error()` when a debugger is attached
 2020-05-03 16:19:42 +00:00
whitequark e9f2d3f009 kernel: Trap in log_error() when a debugger is attached. 
The workflow of debugging fatal pass errors in Yosys is flawed in
three ways:
 1. Running Yosys under a debugger is sufficient for the debugger
    to catch some fatal errors (segfaults, aborts, STL exceptions)
    but not others (`log_error()`, `log_cmd_error()`). This is
    neither obvious nor easy to remember.
 2. To catch Yosys-specific fatal errors, it is necessary to set
    a breakpoint at `logv_error_with_prefix()`, or at least,
    `logv_error()`. This is neither obvious nor easy to remember,
    and GDB's autocomplete takes many seconds to suggest function
    names due to the large amount of symbols in Yosys.
 3. If a breakpoint is not set and Yosys encounters with such
    a fatal error, the process terminates. When debugging a crash
    that takes a long time to reproduce (or a nondeterministic crash)
    this can waste a significant amount of time.

To solve this problem, add a macro `YS_DEBUGTRAP` that acts as a hard
breakpoint (if available), and a macro `YS_DEBUGTRAP_IF_DEBUGGING`
that acts as a hard breakpoint only if debugger is present.

Then, use `YS_DEBUGTRAP_IF_DEBUGGING` in `logv_error_with_prefix()`
to obviate the need for a breakpoint on nearly every platform.

Co-Authored-By: Alberto Gonzalez <boqwxp@airmail.cc>
 2020-05-03 12:02:34 +00:00
Claire Wolf 5c82c19b4b
Merge pull request #2014 from YosysHQ/claire/fixoptalu 
Fix the other "opt_expr -fine" bug introduced in 213a89558
 2020-05-03 11:56:29 +02:00
Eddie Hung db13852ed6 test: add test for #2014 2020-05-02 14:22:37 -07:00
Eddie Hung 7360155459
Merge pull request #2013 from YosysHQ/eddie/aiger_fixes 
aiger: fixes for ports that have start_offset != 0
 2020-05-02 14:16:10 -07:00
Claire Wolf 2285cf1219 Fix the other "opt_expr -fine" bug introduced in 213a89558 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 21:50:43 +02:00
Eddie Hung da7da44919 abc9_ops: -reintegrate to be sensitive to start_offset too 2020-05-02 11:19:04 -07:00
Eddie Hung 2e78daf1ca tests: aiger test for wire->start_offset != 0 2020-05-02 10:00:32 -07:00
Eddie Hung a0afa1787e aiger: fixes for ports that have start_offset != 0 2020-05-02 10:00:32 -07:00
Claire Wolf ca3fc3c882
Merge pull request #2010 from YosysHQ/claire/fixopt 
Fix "opt_expr -fine" bug introduced in 213a89558
 2020-05-02 11:20:02 +02:00
whitequark ff7a8d0e1e Update ABC to include WASI support fixes. 2020-05-02 00:18:33 +00:00
whitequark b36060cc20 Fix WASI builds with abc enabled. 
This PR works around #2011.
 2020-05-01 23:57:35 +00:00
whitequark bbde241942
Merge pull request #2001 from whitequark/wasi 
Add WASI platform support
 2020-05-01 21:28:20 +00:00
Eddie Hung 7f9ecddb7f Add testcase for #2010 2020-05-01 14:07:33 -07:00
Claire Wolf 8ee32adac3 Fix "opt_expr -fine" bug introduced in 213a89558 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-01 20:12:16 +02:00
Claire Wolf 667f38fe53
Merge pull request #1997 from whitequark/document-ootb 
Explain how to do out-of-tree builds in README
 2020-05-01 15:35:33 +02:00
Claire Wolf d047ca8b11
Merge pull request #1981 from YosysHQ/claire/fix1837 
Clear current_scope when done with RTLIL generation
 2020-05-01 14:58:41 +02:00
Alberto Gonzalez b0268b1311
frontend: Include complete source location instead of just location.first_line in frontends/ast/genrtlil.cc. 2020-05-01 07:17:27 +00:00
whitequark b43c282e4e Add WASI platform support. 
This includes the following significant changes:
  * Patching ezsat and minisat to disable resource limiting code
    on WASM/WASI, since the POSIX functions they use are unavailable.
  * Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform
    does not support spawning subprocesses (i.e. Emscripten or WASI).
    This definition hides the definition of `run_command()`.
  * Adding a new Makefile flag, DISABLE_SPAWN, present in the same
    condition. This flag disables all passes that require spawning
    subprocesses for their function.
 2020-04-30 18:56:25 +00:00