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https://github.com/YosysHQ/yosys
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sta: proof of concept to compute arrival times
This commit is contained in:
Eddie Hung
parent
c6b22f5b7d
commit
dedaab3a7d
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@ -339,6 +339,27 @@ pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
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return data;
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}
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void RTLIL::AttrObject::set_intvec_attribute(RTLIL::IdString id, const vector<int> &data)
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{
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std::stringstream attrval;
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for (auto &i : data) {
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if (attrval.tellp() > 0)
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attrval << " ";
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attrval << i;
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}
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attributes[id] = RTLIL::Const(attrval.str());
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}
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vector<int> RTLIL::AttrObject::get_intvec_attribute(RTLIL::IdString id) const
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{
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vector<int> data;
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auto it = attributes.find(id);
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if (it != attributes.end())
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for (const auto &s : split_tokens(attributes.at(id).decode_string()))
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data.push_back(atoi(s.c_str()));
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return data;
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}
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bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
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{
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if (full_selection)
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@ -678,6 +678,9 @@ struct RTLIL::AttrObject
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std::string get_src_attribute() const {
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return get_string_attribute(ID::src);
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}
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void set_intvec_attribute(RTLIL::IdString id, const vector<int> &data);
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vector<int> get_intvec_attribute(RTLIL::IdString id) const;
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};
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struct RTLIL::SigChunk
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@ -39,3 +39,4 @@ OBJS += passes/cmds/bugpoint.o
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endif
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OBJS += passes/cmds/scratchpad.o
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OBJS += passes/cmds/logger.o
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OBJS += passes/cmds/sta.o
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210
passes/cmds/sta.cc
Normal file
210
passes/cmds/sta.cc
Normal file
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@ -0,0 +1,210 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* (C) 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/timinginfo.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct StaWorker
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{
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RTLIL::Design *design;
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RTLIL::Module *module;
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SigMap sigmap;
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dict<SigBit, std::vector<pair<SigBit, int>>> fanouts;
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dict<SigBit, std::pair<SigBit,int>> backtrack;
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std::deque<SigBit> queue;
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dict<SigBit, int> endpoints;
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int maxarrival;
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SigBit maxbit;
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StaWorker(RTLIL::Module *module) : design(module->design), module(module), sigmap(module), maxarrival(0)
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{
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TimingInfo timing;
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for (auto cell : module->cells())
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{
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Module *inst_module = design->module(cell->type);
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log_assert(inst_module);
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if (!inst_module->get_blackbox_attribute()) {
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log_warning("Module '%s' is not a black- nor white-box!\n", log_id(cell->type));
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continue;
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}
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IdString derived_type = inst_module->derive(design, cell->parameters);
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inst_module = design->module(derived_type);
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log_assert(inst_module);
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if (!timing.count(derived_type)) {
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auto &t = timing.setup_module(inst_module);
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if (t.comb.empty() && t.arrival.empty() && t.required.empty())
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log_warning("Module '%s' has no timing arcs!\n", log_id(cell->type));
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}
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auto &t = timing.at(derived_type);
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if (t.comb.empty() && t.arrival.empty() && t.required.empty())
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continue;
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pool<std::pair<SigBit,TimingInfo::NameBit>> src_bits, dst_bits;
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for (auto &conn : cell->connections()) {
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auto rhs = sigmap(conn.second);
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for (auto i = 0; i < GetSize(rhs); i++) {
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const auto &bit = rhs[i];
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if (!bit.wire)
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continue;
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TimingInfo::NameBit namebit(conn.first,i);
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if (cell->input(conn.first)) {
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src_bits.insert(std::make_pair(bit,namebit));
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auto it = t.required.find(namebit);
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if (it == t.required.end())
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continue;
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endpoints[bit] = it->second;
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}
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if (cell->output(conn.first)) {
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dst_bits.insert(std::make_pair(bit,namebit));
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auto it = t.arrival.find(namebit);
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if (it == t.arrival.end())
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continue;
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auto arrivals = bit.wire->get_intvec_attribute(ID(sta_arrival));
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if (arrivals.empty())
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arrivals = std::vector<int>(GetSize(bit.wire), -1);
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else
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log_assert(GetSize(arrivals) == GetSize(bit.wire));
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arrivals[bit.offset] = it->second;
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bit.wire->set_intvec_attribute(ID(sta_arrival), arrivals);
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queue.emplace_back(bit);
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}
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}
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}
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for (const auto &s : src_bits)
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for (const auto &d : dst_bits) {
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auto it = t.comb.find(TimingInfo::BitBit(s.second,d.second));
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if (it == t.comb.end())
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continue;
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fanouts[s.first].emplace_back(d.first,it->second);
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}
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}
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for (auto port_name : module->ports) {
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auto wire = module->wire(port_name);
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if (!wire->port_input)
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continue;
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for (const auto &b : sigmap(wire))
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queue.emplace_back(b);
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// All primary inputs to arrive at time zero
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wire->set_intvec_attribute(ID(sta_arrival), std::vector<int>(GetSize(wire), 0));
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}
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}
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void run()
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{
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while (!queue.empty()) {
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auto b = queue.front();
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queue.pop_front();
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auto it = fanouts.find(b);
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if (it == fanouts.end())
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continue;
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const auto& src_arrivals = b.wire->get_intvec_attribute(ID(sta_arrival));
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log_assert(GetSize(src_arrivals) == GetSize(b.wire));
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auto src_arrival = src_arrivals[b.offset];
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for (const auto &d : it->second) {
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auto dst_arrivals = d.first.wire->get_intvec_attribute(ID(sta_arrival));
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if (dst_arrivals.empty())
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dst_arrivals = std::vector<int>(GetSize(d.first.wire), -1);
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else
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log_assert(GetSize(dst_arrivals) == GetSize(d.first.wire));
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auto &dst_arrival = dst_arrivals[d.first.offset];
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auto new_arrival = src_arrival + d.second + endpoints.at(d.first, 0);
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if (dst_arrival < new_arrival) {
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dst_arrival = std::max(dst_arrival, new_arrival);
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if (dst_arrival > maxarrival) {
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maxarrival = dst_arrival;
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maxbit = d.first;
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}
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d.first.wire->set_intvec_attribute(ID(sta_arrival), dst_arrivals);
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queue.emplace_back(d.first);
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backtrack[d.first] = std::make_pair(b, src_arrival);
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}
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}
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}
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log("Latest arrival time in '%s' is %d:\n", log_id(module), maxarrival);
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auto b = maxbit;
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auto arrival = maxarrival;
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auto it = backtrack.find(b);
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while (it != backtrack.end()) {
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log(" %6d %s\n", arrival, log_signal(b));
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std::tie(b,arrival) = it->second;
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it = backtrack.find(b);
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}
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log(" %6d %s\n", arrival, log_signal(b));
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}
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};
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struct StaPass : public Pass {
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StaPass() : Pass("sta", "perform static timing analysis") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" sta [options] [selection]\n");
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log("\n");
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log("This command performs static timing analysis on the design. (Only considers\n");
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log("paths within a single module, so the design must be flattened.)\n");
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log("\n");
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log(" -TODO\n");
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log(" TODO\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing STA pass (static timing analysis).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-TODO") {
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (Module *module : design->selected_modules())
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{
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if (module->has_processes_warn())
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continue;
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StaWorker worker(module);
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worker.run();
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}
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}
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} StaPass;
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PRIVATE_NAMESPACE_END
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