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https://github.com/YosysHQ/yosys
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sta: use ID::sta_arrival
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@ -154,6 +154,7 @@ X(SRC_EN)
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X(SRC_PEN)
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X(SRC_POL)
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X(SRC_WIDTH)
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X(sta_arrival)
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X(STATE_BITS)
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X(STATE_NUM)
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X(STATE_NUM_LOG2)
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@ -141,8 +141,8 @@ struct TimingInfo
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}
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}
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else if (cell->type == ID($specrule)) {
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auto type = cell->getParam(ID::TYPE).decode_string();
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if (type != "$setup" && type != "$setuphold")
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IdString type = cell->getParam(ID::TYPE).decode_string();
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if (type != ID($setup) && type != ID($setuphold))
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continue;
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auto src = cell->getPort(ID::SRC);
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auto dst = cell->getPort(ID::DST).as_bit();
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@ -135,7 +135,7 @@ struct StaWorker
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for (const auto &b : sigmap(wire))
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queue.emplace_back(b);
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// All primary inputs to arrive at time zero
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wire->set_intvec_attribute(ID(sta_arrival), std::vector<int>(GetSize(wire), 0));
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wire->set_intvec_attribute(ID::sta_arrival, std::vector<int>(GetSize(wire), 0));
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}
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if (wire->port_output)
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for (const auto &b : sigmap(wire))
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@ -152,12 +152,12 @@ struct StaWorker
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auto it = data.find(b);
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if (it == data.end())
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continue;
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const auto& src_arrivals = b.wire->get_intvec_attribute(ID(sta_arrival));
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const auto& src_arrivals = b.wire->get_intvec_attribute(ID::sta_arrival);
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log_assert(GetSize(src_arrivals) == GetSize(b.wire));
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auto src_arrival = src_arrivals[b.offset];
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for (const auto &d : it->second.fanouts) {
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const auto &dst_bit = std::get<0>(d);
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auto dst_arrivals = dst_bit.wire->get_intvec_attribute(ID(sta_arrival));
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auto dst_arrivals = dst_bit.wire->get_intvec_attribute(ID::sta_arrival);
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if (dst_arrivals.empty())
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dst_arrivals = std::vector<int>(GetSize(dst_bit.wire), -1);
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else
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@ -166,7 +166,7 @@ struct StaWorker
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auto new_arrival = src_arrival + std::get<1>(d);
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if (dst_arrival < new_arrival) {
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dst_arrival = std::max(dst_arrival, new_arrival);
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dst_bit.wire->set_intvec_attribute(ID(sta_arrival), dst_arrivals);
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dst_bit.wire->set_intvec_attribute(ID::sta_arrival, dst_arrivals);
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queue.emplace_back(dst_bit);
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data[dst_bit].backtrack = b;
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@ -194,7 +194,7 @@ struct StaWorker
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}
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auto jt = data.find(b);
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while (jt != data.end()) {
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int arrival = b.wire->get_intvec_attribute(ID(sta_arrival))[b.offset];
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int arrival = b.wire->get_intvec_attribute(ID::sta_arrival)[b.offset];
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if (jt->second.driver) {
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log(" %s\n", log_signal(b));
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log(" %6d %s (%s.%s->%s)\n", arrival, log_id(jt->second.driver), log_id(jt->second.driver->type), log_id(jt->second.src_port), log_id(jt->second.dst_port));
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@ -210,11 +210,11 @@ struct StaWorker
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std::map<int, unsigned> arrival_histogram;
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for (const auto &i : endpoints) {
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const auto &b = i.first;
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if (!b.wire->attributes.count(ID(sta_arrival))) {
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if (!b.wire->attributes.count(ID::sta_arrival)) {
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log_warning("Wire %s.%s has no (* sta_arrival *) value.\n", log_id(module), log_signal(b));
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continue;
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}
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auto arrival = b.wire->get_intvec_attribute(ID(sta_arrival))[b.offset];
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auto arrival = b.wire->get_intvec_attribute(ID::sta_arrival)[b.offset];
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if (arrival < 0) {
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// FIXME: Might be an unreachable signal
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// Might be a constant driven signal (e.g. through OBUF)
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