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techlibs/common/simlib.v: EN_{SRC,DST} -> {SRC,DST}_EN

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Eddie Hung 2020-05-05 08:30:36 -07:00
parent 5a33f089bf
commit fd72c1c995
1 changed files with 2 additions and 2 deletions
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4
techlibs/common/simlib.v
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@ -1445,7 +1445,7 @@ endmodule
// --------------------------------------------------------
module \$specrule (EN_SRC, EN_DST, SRC, DST);
module \$specrule (SRC_EN, DST_EN, SRC, DST);
parameter TYPE = "";
parameter T_LIMIT = 0;
@ -1460,7 +1460,7 @@ parameter SRC_POL = 0;
parameter DST_PEN = 0;
parameter DST_POL = 0;
input EN_SRC, EN_DST;
input SRC_EN, DST_EN;
input [SRC_WIDTH-1:0] SRC;
input [DST_WIDTH-1:0] DST;