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https://github.com/YosysHQ/yosys
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sta: print out arrival histogram
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@ -32,7 +32,7 @@ struct StaWorker
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SigMap sigmap;
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dict<SigBit, std::vector<pair<SigBit, int>>> fanouts;
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dict<SigBit, std::pair<SigBit,int>> backtrack;
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dict<SigBit, SigBit> backtrack;
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std::deque<SigBit> queue;
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dict<SigBit, int> endpoints;
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@ -149,21 +149,62 @@ struct StaWorker
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}
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d.first.wire->set_intvec_attribute(ID(sta_arrival), dst_arrivals);
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queue.emplace_back(d.first);
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backtrack[d.first] = std::make_pair(b, src_arrival);
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backtrack[d.first] = b;
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}
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}
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}
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log("Latest arrival time in '%s' is %d:\n", log_id(module), maxarrival);
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auto b = maxbit;
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auto arrival = maxarrival;
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int arrival = maxarrival;
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auto it = backtrack.find(b);
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while (it != backtrack.end()) {
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log(" %6d %s\n", arrival, log_signal(b));
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std::tie(b,arrival) = it->second;
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b = it->second;
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arrival = b.wire->get_intvec_attribute(ID(sta_arrival))[b.offset];
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it = backtrack.find(b);
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}
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log(" %6d %s\n", arrival, log_signal(b));
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std::map<int, unsigned> arrival_histogram;
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for (const auto &i : endpoints) {
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const auto &b = i.first;
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auto arrival = b.wire->get_intvec_attribute(ID(sta_arrival))[b.offset];
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arrival += i.second;
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arrival_histogram[arrival]++;
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}
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for (auto port_name : module->ports) {
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auto wire = module->wire(port_name);
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if (!wire->port_output)
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continue;
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for (auto arrival : wire->get_intvec_attribute(ID(sta_arrival)))
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arrival_histogram[arrival]++;
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}
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// Adapted from https://github.com/YosysHQ/nextpnr/blob/affb12cc27ebf409eade062c4c59bb98569d8147/common/timing.cc#L946-L969
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if (arrival_histogram.size() > 0) {
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unsigned num_bins = 20;
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unsigned bar_width = 60;
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auto min_arrival = arrival_histogram.begin()->first;
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auto max_arrival = arrival_histogram.rbegin()->first;
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auto bin_size = std::max<unsigned>(1, ceil((max_arrival - min_arrival + 1) / float(num_bins)));
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std::vector<unsigned> bins(num_bins);
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unsigned max_freq = 0;
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for (const auto &i : arrival_histogram) {
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auto &bin = bins[(i.first - min_arrival) / bin_size];
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bin += i.second;
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max_freq = std::max(max_freq, bin);
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}
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bar_width = std::min(bar_width, max_freq);
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log("\n");
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log("Arrival histogram:\n");
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log(" legend: * represents %d endpoint(s)\n", max_freq / bar_width);
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log(" + represents [1,%d) endpoint(s)\n", max_freq / bar_width);
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for (int i = num_bins-1; i >= 0; --i)
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log("[%6d, %6d) |%s%c\n", min_arrival + bin_size * i, min_arrival + bin_size * (i + 1),
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std::string(bins[i] * bar_width / max_freq, '*').c_str(),
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(bins[i] * bar_width) % max_freq > 0 ? '+' : ' ');
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}
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}
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};
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