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sta: assume input-less modules to be constant drivers and don't warn ...
if no timing arcs. Also handle undefined modules with a warning
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@ -52,6 +52,7 @@ struct TimingInfo
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{
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dict<BitBit, int> comb;
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dict<NameBit, std::pair<int,NameBit>> arrival, required;
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bool has_inputs;
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};
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dict<RTLIL::IdString, ModuleTiming> data;
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@ -167,6 +168,14 @@ struct TimingInfo
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}
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}
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for (auto port_name : module->ports) {
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auto wire = module->wire(port_name);
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if (wire->port_input) {
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t.has_inputs = true;
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break;
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}
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}
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return t;
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}
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@ -60,10 +60,13 @@ struct StaWorker
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for (auto cell : module->cells())
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{
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Module *inst_module = design->module(cell->type);
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log_assert(inst_module);
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if (!inst_module) {
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log_warning("Cell type '%s' not recognised! Ignoring.\n", log_id(cell->type));
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continue;
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}
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if (!inst_module->get_blackbox_attribute()) {
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log_warning("Module '%s' is not a black- nor white-box!\n", log_id(cell->type));
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log_warning("Cell type '%s' is not a black- nor white-box! Ignoring.\n", log_id(cell->type));
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continue;
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}
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@ -73,7 +76,7 @@ struct StaWorker
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if (!timing.count(derived_type)) {
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auto &t = timing.setup_module(inst_module);
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if (t.comb.empty() && t.arrival.empty() && t.required.empty())
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if (t.has_inputs && t.comb.empty() && t.arrival.empty() && t.required.empty())
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log_warning("Module '%s' has no timing arcs!\n", log_id(cell->type));
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}
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@ -40,4 +40,42 @@ endmodule
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EOT
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sta
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design -reset
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read_verilog -specify <<EOT
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module buffer(input i, output o);
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specify
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(i => o) = 10;
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endspecify
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endmodule
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module top(input i, output o, p);
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buffer b(.i(i), .o(o));
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const0 c(.o(p));
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endmodule
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EOT
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logger -expect warning "Cell type 'const0' not recognised! Ignoring\." 1
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sta
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design -reset
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read_verilog -specify <<EOT
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module buffer(input i, output o);
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specify
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(i => o) = 10;
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endspecify
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endmodule
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module const0(output o);
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endmodule
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module top(input i, output o, p);
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buffer b(.i(i), .o(o));
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const0 c(.o(p));
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endmodule
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EOT
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sta
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logger -expect-no-warnings
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