WIP: fpga support and arty a7 100t #38

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programmerjake wants to merge 12 commits from programmerjake/fayalite:fpga-support-and-arty-a7-100t into master

pull from: programmerjake/fayalite:fpga-support-and-arty-a7-100t

merge into: libre-chip:master

libre-chip:master

libre-chip:square-brackets-generics-experiment

libre-chip:runtime-generics

libre-chip:type-deduction

Conversation 0 Commits 12 Files changed 34 +7955 -1195

programmerjake commented 2025-10-10 08:16:18 +00:00

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I got blinky to work on the Arty A7 100T! (though the reset input is inverted so it only works while you hold down the reset button.)

Commands I used:

cargo run --example blinky -- yosys-nextpnr-xray --nextpnr-xilinx-chipdb-dir ~/projects/libre-chip-deps/nextpnr-xilinx/xilinx/ --prjxray-db-dir ~/projects/libre-chip-deps/prjxray-db/ --device xc7a100ticsg324-1L -o target/blinky-out --clock-frequency=$((1000*1000*100))
sudo openFPGALoader --board arty_a7_100t target/blinky-out/blinky.bit

Fixes: libre-chip/grant-tracking#4
Fixes: libre-chip/grant-tracking#6

It still needs:

• system for generating .xdc constraint file from annotations on I/O of the main module, currently I hard-coded a minimal file for blinky
• system for getting the available peripherals on the current board and wiring them up to the rest of your circuit and generating those I/O annotations

done:

• docs or a script to build all the dependencies -- https://git.libre-chip.org/libre-chip/fayalite-deps
• building a .bit file in CI

I got blinky to work on the Arty A7 100T! (though the reset input is inverted so it only works while you hold down the reset button.) Commands I used: ```bash cargo run --example blinky -- yosys-nextpnr-xray --nextpnr-xilinx-chipdb-dir ~/projects/libre-chip-deps/nextpnr-xilinx/xilinx/ --prjxray-db-dir ~/projects/libre-chip-deps/prjxray-db/ --device xc7a100ticsg324-1L -o target/blinky-out --clock-frequency=$((1000*1000*100)) sudo openFPGALoader --board arty_a7_100t target/blinky-out/blinky.bit ``` Fixes: libre-chip/grant-tracking#4 Fixes: libre-chip/grant-tracking#6 It still needs: * [ ] system for generating .xdc constraint file from annotations on I/O of the main module, currently I hard-coded a minimal file for blinky * [ ] system for getting the available peripherals on the current board and wiring them up to the rest of your circuit and generating those I/O annotations done: * [x] docs or a script to build all the dependencies -- https://git.libre-chip.org/libre-chip/fayalite-deps * [x] building a .bit file in CI

programmerjake added 8 commits 2025-10-10 08:16:18 +00:00

WIP adding FPGA support -- build module should be complete cec0eb410e

added automatically-added dependencies; added caching for external jobs ecc5ffd9eb

WIP converting from cli.rs to build/*.rs 90aed1615e

switch to using new crate::build system 01ba321014

mark create-unix-shell-script as incomplete in CLI f152d3e5f3

change cache directory name to be fayalite-specific 0306d3b07d

WIP build Xilinx FPGA dependencies in CI 338ce7ed32

WIP adding yosys-nextpnr-xray xilinx fpga toolchain -- blinky works on arty a7 100t (except for inverted reset) 74ad0e104e

programmerjake added 1 commit 2025-10-11 00:11:27 +00:00

fix redirects adf485c44a

programmerjake added 1 commit 2025-10-11 00:58:42 +00:00

try building .bit file 97878e100a

programmerjake added 1 commit 2025-10-14 10:48:05 +00:00

generate Arty A7 100T .bit file for blinky example in CI f310532eaa

programmerjake force-pushed fpga-support-and-arty-a7-100t from f310532eaa to faf1e5113c 2025-10-14 10:50:10 +00:00 Compare

programmerjake added 1 commit 2025-10-15 11:12:23 +00:00

WIP adding annotations for generating the .xdc file for yosys-nextpnr-prjxray c2df30f844

programmerjake force-pushed fpga-support-and-arty-a7-100t from c2df30f844 to 676c1e3b7d 2025-10-15 11:29:32 +00:00 Compare

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Reference: libre-chip/fayalite#38

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