fpga support and arty a7 100t #38

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programmerjake merged 20 commits from programmerjake/fayalite:fpga-support-and-arty-a7-100t into master 2025-10-22 05:36:13 +00:00

Conversation 3 Commits 20 Files changed 48 +11787 -1318

programmerjake commented 2025-10-10 08:16:18 +00:00

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I got blinky to work on the Arty A7 100T! (though the reset input is inverted so it only works while you hold down the reset button -- fixed)

Commands to use:

podman run --rm --security-opt label=disable --volume="$(pwd):$(pwd)" --volume="$(realpath ~/.cargo):/root/.cargo" -w="$(pwd)" -it git.libre-chip.org/libre-chip/fayalite-deps:latest cargo run --example blinky yosys-nextpnr-xray --nextpnr-xilinx-chipdb-dir /opt/fayalite-deps/nextpnr-xilinx/xilinx --prjxray-db-dir /opt/fayalite-deps/prjxray-db --platform arty-a7-100t -o target/blinky-out
sudo openFPGALoader --board arty_a7_100t target/blinky-out/blinky.bit

Fixes: libre-chip/grant-tracking#4
Fixes: libre-chip/grant-tracking#6

It still needs:

done:

• determine why rgb led is blinking randomly like there's a loose connection or something -- #38 (comment)
• system for generating .xdc constraint file from annotations on I/O of the main module, currently I hard-coded a minimal file for blinky
• system for getting the available peripherals on the current board and wiring them up to the rest of your circuit and generating those I/O annotations
• docs or a script to build all the dependencies -- https://git.libre-chip.org/libre-chip/fayalite-deps
• building a .bit file in CI

I got blinky to work on the Arty A7 100T! (~~though the reset input is inverted so it only works while you hold down the reset button~~ -- fixed) Commands to use: ```bash podman run --rm --security-opt label=disable --volume="$(pwd):$(pwd)" --volume="$(realpath ~/.cargo):/root/.cargo" -w="$(pwd)" -it git.libre-chip.org/libre-chip/fayalite-deps:latest cargo run --example blinky yosys-nextpnr-xray --nextpnr-xilinx-chipdb-dir /opt/fayalite-deps/nextpnr-xilinx/xilinx --prjxray-db-dir /opt/fayalite-deps/prjxray-db --platform arty-a7-100t -o target/blinky-out sudo openFPGALoader --board arty_a7_100t target/blinky-out/blinky.bit ``` Fixes: libre-chip/grant-tracking#4 Fixes: libre-chip/grant-tracking#6 It still needs: done: * [x] determine why rgb led is blinking randomly like there's a loose connection or something -- https://git.libre-chip.org/libre-chip/fayalite/pulls/38#issuecomment-287 * [x] system for generating .xdc constraint file from annotations on I/O of the main module, currently I hard-coded a minimal file for blinky * [x] system for getting the available peripherals on the current board and wiring them up to the rest of your circuit and generating those I/O annotations * [x] docs or a script to build all the dependencies -- https://git.libre-chip.org/libre-chip/fayalite-deps * [x] building a .bit file in CI

programmerjake added 8 commits 2025-10-10 08:16:18 +00:00

WIP adding FPGA support -- build module should be complete cec0eb410e

added automatically-added dependencies; added caching for external jobs ecc5ffd9eb

WIP converting from cli.rs to build/*.rs 90aed1615e

switch to using new crate::build system 01ba321014

mark create-unix-shell-script as incomplete in CLI f152d3e5f3

change cache directory name to be fayalite-specific 0306d3b07d

WIP build Xilinx FPGA dependencies in CI 338ce7ed32

WIP adding yosys-nextpnr-xray xilinx fpga toolchain -- blinky works on arty a7 100t (except for inverted reset) 74ad0e104e

programmerjake added 1 commit 2025-10-11 00:11:27 +00:00

fix redirects adf485c44a

programmerjake added 1 commit 2025-10-11 00:58:42 +00:00

try building .bit file 97878e100a

programmerjake added 1 commit 2025-10-14 10:48:05 +00:00

generate Arty A7 100T .bit file for blinky example in CI f310532eaa

programmerjake force-pushed fpga-support-and-arty-a7-100t from f310532eaa to faf1e5113c 2025-10-14 10:50:10 +00:00 Compare

programmerjake added 1 commit 2025-10-15 11:12:23 +00:00

WIP adding annotations for generating the .xdc file for yosys-nextpnr-prjxray c2df30f844

programmerjake force-pushed fpga-support-and-arty-a7-100t from c2df30f844 to 676c1e3b7d 2025-10-15 11:29:32 +00:00 Compare

programmerjake added 1 commit 2025-10-16 11:34:27 +00:00

do some clean up a565be1b09

programmerjake added 1 commit 2025-10-16 12:10:30 +00:00

group all xilinx annotations together def406ab52

programmerjake added 1 commit 2025-10-17 12:55:37 +00:00

WIP adding Platform 3f5dd61e46

programmerjake added 2 commits 2025-10-18 01:00:27 +00:00

move vendor module to top level 4d54f903be

WIP adding peripherals 2848f3dee4

programmerjake force-pushed fpga-support-and-arty-a7-100t from 2848f3dee4 to d2efb94686 2025-10-19 06:24:34 +00:00 Compare

programmerjake force-pushed fpga-support-and-arty-a7-100t from d2efb94686 to 917a603b34 2025-10-20 05:25:35 +00:00 Compare

programmerjake added 1 commit 2025-10-20 06:11:43 +00:00

WIP adding xdc create_clock -- nextpnr-xilinx currently ignores it cf7436b7cd

programmerjake force-pushed fpga-support-and-arty-a7-100t from cf7436b7cd to 2bdc8a7c72 2025-10-20 06:13:37 +00:00 Compare

programmerjake changed title from WIP: fpga support and arty a7 100t to fpga support and arty a7 100t 2025-10-20 10:36:59 +00:00

programmerjake commented 2025-10-20 10:40:52 +00:00

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I got everything to work except that either blinky has an error or the board is broken -- one of the rgb leds blinks randomly as if there's a broken connection somewhere.

also I need to adjust the generated xdc so the clock properly gets the frequency constraint -- though afaict that isn't the cause of the random blinking since nextpnr-xilinx says it works up to >150MHz where the clock is only 100Mhz.

I got everything to work except that either blinky has an error or the board is broken -- one of the rgb leds blinks randomly as if there's a broken connection somewhere. also I need to adjust the generated xdc so the clock properly gets the frequency constraint -- though afaict that isn't the cause of the random blinking since nextpnr-xilinx says it works up to >150MHz where the clock is only 100Mhz.

programmerjake commented 2025-10-22 03:02:43 +00:00

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@programmerjake wrote in #38 (comment):

I got everything to work except that either blinky has an error or the board is broken -- one of the rgb leds blinks randomly as if there's a broken connection somewhere.

I checked it with my oscilloscope and it seems the green led has a broken connection, the transistor powering it and everything before then works fine, so I'm satisfied it's not caused by the FPGA so I'll just ignore it.

@programmerjake wrote in https://git.libre-chip.org/libre-chip/fayalite/pulls/38#issuecomment-286: > I got everything to work except that either blinky has an error or the board is broken -- one of the rgb leds blinks randomly as if there's a broken connection somewhere. I checked it with my oscilloscope and it seems the green led has a broken connection, the transistor powering it and everything before then works fine, so I'm satisfied it's not caused by the FPGA so I'll just ignore it.

programmerjake added 2 commits 2025-10-22 05:24:14 +00:00

switch to using verilog for reset synchronizer so we can use attributes on FDPE instances 409992961c

properly handle all XilinxAnnotations, this makes nextpnr-xilinx properly pick up the clock frequency c6feea6d51

programmerjake commented 2025-10-22 05:29:35 +00:00

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@programmerjake wrote in #38 (comment):

also I need to adjust the generated xdc so the clock properly gets the frequency constraint -- though afaict that isn't the cause of the random blinking since nextpnr-xilinx says it works up to >150MHz where the clock is only 100Mhz.

done.

@programmerjake wrote in https://git.libre-chip.org/libre-chip/fayalite/pulls/38#issuecomment-286: > also I need to adjust the generated xdc so the clock properly gets the frequency constraint -- though afaict that isn't the cause of the random blinking since nextpnr-xilinx says it works up to >150MHz where the clock is only 100Mhz. done.

programmerjake merged commit c6feea6d51 into master 2025-10-22 05:36:13 +00:00

programmerjake deleted branch fpga-support-and-arty-a7-100t 2025-10-22 05:36:14 +00:00

programmerjake referenced this pull request from libre-chip/grant-tracking 2025-10-22 06:15:57 +00:00

NLnet 2024-12-324 Write support for board interface descriptions and the code for running the FPGA toolchain (similar to the existing code for running SymbiYosys -- the current formal verification toolchain). #4

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Reference: libre-chip/fayalite#38

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