Initial work on representing HDL and formal verification in Rocq. #56

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programmerjake merged 3 commits from cesar/fayalite:rocq_hdl into master 2025-12-09 16:34:36 +00:00
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I guess I'm ready to push my work on Rocq so far.

I guess I'm ready to push my work on Rocq so far.
cesar added 2 commits 2025-12-09 01:11:41 +00:00
Starts with a very simple example, including a proof by induction.
Demonstrates state with multiple variables and hidden state.
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e54558d848

as you probably saw, you'll also need to add the code for checking for copyright headers to
scripts/check-copyright.sh

as you probably saw, you'll also need to add the code for checking for copyright headers to `scripts/check-copyright.sh`
cesar added 1 commit 2025-12-09 10:48:05 +00:00
Check copyright header in Rocq files.
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e4210a672f
If we ever add Verilog files, we can "or" both results, I guess.
programmerjake merged commit e4210a672f into master 2025-12-09 16:34:36 +00:00
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Reference: libre-chip/fayalite#56
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