programmerjake
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  • Joined on 2024-07-08
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programmerjake deleted branch adding-simulator from libre-chip/fayalite 2024-12-18 10:03:37 +00:00
programmerjake merged pull request libre-chip/fayalite#8 2024-12-18 10:03:36 +00:00
sim: add SimValue and reading/writing more than just a scalar
programmerjake created pull request libre-chip/fayalite#8 2024-12-18 09:42:02 +00:00
sim: add SimValue and reading/writing more than just a scalar
programmerjake created branch adding-simulator in libre-chip/fayalite 2024-12-18 09:40:53 +00:00
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-18 09:40:53 +00:00
21c73051ec sim: add SimValue and reading/writing more than just a scalar
programmerjake pushed to master at libre-chip/server-setup 2024-12-17 01:03:31 +00:00
e152c2d160 upgrade mail server to v0.10.7
programmerjake pushed to master at libre-chip/cpu 2024-12-16 04:33:20 +00:00
1761d7094e update to latest fayalite and match rust version
programmerjake pushed to master at libre-chip/fayalite 2024-12-16 04:06:51 +00:00
304d8da0e8 Merge remote-tracking branch 'origin/master' into adding-simulator
2af38de900 add more memory tests
c756aeec70 tests/sim: add test for memory rw port
903ca1bf30 sim: simple memory test works!
8d030ac65d sim/interpreter: add addresses to instruction listing
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programmerjake deleted branch adding-simulator from libre-chip/fayalite 2024-12-16 04:06:51 +00:00
programmerjake merged pull request libre-chip/fayalite#3 2024-12-16 04:06:49 +00:00
add a simulator
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-13 23:07:26 +00:00
304d8da0e8 Merge remote-tracking branch 'origin/master' into adding-simulator
2e7d685dc7 add module exercising formal verification of memories
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programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-13 23:05:22 +00:00
2af38de900 add more memory tests
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-13 04:51:11 +00:00
c756aeec70 tests/sim: add test for memory rw port
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-13 03:48:20 +00:00
903ca1bf30 sim: simple memory test works!
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-13 00:27:48 +00:00
8d030ac65d sim/interpreter: add addresses to instruction listing
562c479b62 sim/interpreter: fix StatePartLayout name in debug output
Compare 2 commits »
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-12 07:29:05 +00:00
393f78a14d sim: add WIP memory test
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-11 08:01:40 +00:00
8616ee4737 tests/sim: test_enums works!
5087f16099 sim: fix assignments graph by properly including conditions as assignment inputs
Compare 2 commits »
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-11 07:41:27 +00:00
6b31e6d515 sim: add .dot output for Assignments graph for debugging
564ccb30bc sim/vcd: fix variable identifiers to follow verilog rules
ca759168ff tests/sim: add WIP test for enums
Compare 3 commits »
programmerjake commented on pull request libre-chip/fayalite#3 2024-12-10 07:14:50 +00:00
add a simulator

I think this should be complete enough to merge once I add tests for enums and memories.

there are a few missing minor features still that I probably won't implement before merging:

  • proper…
programmerjake pushed to adding-simulator at libre-chip/fayalite 2024-12-10 07:03:39 +00:00
e4cf66adf8 sim: implement memories, still needs testing
cd0dd7b7ee change memory write latency to NonZeroUsize to match read latency being usize
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