programmerjake
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  • Joined on 2024-07-08
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programmerjake merged pull request libre-chip/fayalite#16 2025-01-16 03:12:04 +00:00
sim: fix "label address not set" bug when the last Assignment is conditional
programmerjake created pull request libre-chip/fayalite#16 2025-01-16 03:07:51 +00:00
sim: fix "label address not set" bug when the last Assignment is conditional
programmerjake created branch fix_label_address_not_set_bug in programmerjake/fayalite 2025-01-16 03:06:35 +00:00
programmerjake pushed to fix_label_address_not_set_bug at programmerjake/fayalite 2025-01-16 03:06:35 +00:00
d4ea826051 sim: fix "label address not set" bug when the last Assignment is conditional
404a2ee043 tests/sim: add test_array_rw
e3a2ccd41c properly handle duplicate names in vcd
3771cea78e Gather the FIFO debug ports in a bundle
dcf865caec Add assertions and debug ports in order for the FIFO to pass induction
Compare 10 commits »
programmerjake pushed to master at libre-chip/cpu 2025-01-13 06:13:15 +00:00
5f7766777a working on reg_alloc -- selected_unit_nums should be correct now
programmerjake deleted branch tests_sim_add_test_array_rw from programmerjake/fayalite 2025-01-13 06:02:21 +00:00
programmerjake pushed to master at libre-chip/fayalite 2025-01-13 06:02:20 +00:00
404a2ee043 tests/sim: add test_array_rw
programmerjake merged pull request libre-chip/fayalite#15 2025-01-13 06:02:20 +00:00
tests/sim: add test_array_rw
programmerjake created pull request libre-chip/fayalite#15 2025-01-13 05:40:16 +00:00
tests/sim: add test_array_rw
programmerjake pushed to tests_sim_add_test_array_rw at programmerjake/fayalite 2025-01-13 05:39:10 +00:00
404a2ee043 tests/sim: add test_array_rw
programmerjake created branch tests_sim_add_test_array_rw in programmerjake/fayalite 2025-01-13 05:37:51 +00:00
programmerjake pushed to tests_sim_add_test_array_rw at programmerjake/fayalite 2025-01-13 05:37:51 +00:00
9e30a58982 tests/sim: add test_array_rw
e3a2ccd41c properly handle duplicate names in vcd
3771cea78e Gather the FIFO debug ports in a bundle
dcf865caec Add assertions and debug ports in order for the FIFO to pass induction
31d01046a8 Initial queue formal proof based on one-entry FIFO equivalence
Compare 10 commits »
programmerjake pushed to master at libre-chip/cpu 2025-01-10 07:38:35 +00:00
89717f8916 update to latest version of fayalite
programmerjake pushed to master at libre-chip/fayalite 2025-01-10 07:11:45 +00:00
e3a2ccd41c properly handle duplicate names in vcd
programmerjake deleted branch vcd-handle-duplicate-names from programmerjake/fayalite 2025-01-10 07:11:45 +00:00
programmerjake merged pull request libre-chip/fayalite#14 2025-01-10 07:11:44 +00:00
properly handle duplicate names in vcd
programmerjake created pull request libre-chip/fayalite#14 2025-01-10 06:55:35 +00:00
properly handle duplicate names in vcd
programmerjake created branch vcd-handle-duplicate-names in programmerjake/fayalite 2025-01-10 06:53:09 +00:00
programmerjake pushed to vcd-handle-duplicate-names at programmerjake/fayalite 2025-01-10 06:53:09 +00:00
e3a2ccd41c properly handle duplicate names in vcd
3771cea78e Gather the FIFO debug ports in a bundle
dcf865caec Add assertions and debug ports in order for the FIFO to pass induction
31d01046a8 Initial queue formal proof based on one-entry FIFO equivalence
c16726cee6 fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s
Compare 10 commits »
programmerjake pushed to master at libre-chip/cpu 2025-01-10 03:58:23 +00:00
24a8b4b71b update fayalite to latest git