programmerjake
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  • Joined on 2024-07-08
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programmerjake closed issue libre-chip/grant-tracking#7 2025-09-09 05:35:24 +00:00
NLnet 2024-12-324 Add to the simulator in Fayalite the ability to transfer non-HDL data (e.g. HashMap) through the digital signalling mechanism, this allows using those data types when writing procedural models.
programmerjake pushed to sim-non-hdl-data at programmerjake/fayalite 2025-09-09 05:20:54 +00:00
db9b1c202c add simulator support for sim-only values
d3dd66cbf0 add rust-src component in CI for consistent error messages
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programmerjake pushed to sim-non-hdl-data at programmerjake/fayalite 2025-09-09 05:04:12 +00:00
9334dff776 add simulator support for sim-only values
programmerjake created pull request libre-chip/fayalite#35 2025-09-06 02:26:26 +00:00
WIP: add support for simulator-only values
programmerjake pushed to sim-non-hdl-data at programmerjake/fayalite 2025-09-06 02:21:42 +00:00
9dd3b7e7e4 add simulator support for sim-only values -- still needs tests
b5b1ee866c converted to using get_state_part_kinds!
f0e3aef061 add get_state_part_kinds! macro
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programmerjake pushed to sim-non-hdl-data at programmerjake/fayalite 2025-09-06 02:06:13 +00:00
8117aab21f add simulator support for sim-only values -- still needs tests
programmerjake pushed to sim-non-hdl-data at programmerjake/fayalite 2025-09-05 22:55:36 +00:00
c8ab70d32f WIP making progress
1fde884e48 converted to using get_state_part_kinds!
9055713ff2 add get_state_part_kinds! macro
fc7ab51620 add StatePartEnum/TypePartEnum
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programmerjake pushed to sim-non-hdl-data at programmerjake/fayalite 2025-09-03 09:56:42 +00:00
9b12ff54e6 WIP making progress
programmerjake pushed to sim-non-hdl-data at programmerjake/fayalite 2025-09-02 07:42:19 +00:00
4b4ef4b459 WIP making progress
programmerjake created branch sim-non-hdl-data in programmerjake/fayalite 2025-09-01 11:47:26 +00:00
programmerjake pushed to sim-non-hdl-data at programmerjake/fayalite 2025-09-01 11:47:26 +00:00
ab21db4103 WIP switched to OpaqueSimValueWriter
6d36698adf move public paths of sim::{Compiled,Compiler} to sim::compiler
e7e831cf00 split out simulator compiler into a separate module
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programmerjake pushed to master at programmerjake/fayalite 2025-08-27 01:14:47 +00:00
4008c311bf format code after switching to edition 2024
ef85d11327 try to get actions to run
ae7c4be9dc remove get_many_mut since it was stabilized in std as get_disjoint_mut
65f9ab32f4 switch to edition 2024
67e66ac3bd upgrade to rust 1.89.0
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programmerjake deleted branch add-structure from programmerjake/grant-tracking 2025-08-26 08:00:53 +00:00
programmerjake merged pull request libre-chip/grant-tracking#1 2025-08-26 08:00:52 +00:00
fill out grant tracking structure
programmerjake pushed to master at libre-chip/grant-tracking 2025-08-26 08:00:52 +00:00
fc04ac0f76 add rest of issues
f9bff4c415 final script fixes
cc7aa3c7b1 dump expected issue contents even when issue doesn't yet exist
fbdcceaea2 add checks for forgejo issues and projects
d02476d925 link to issue and project
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programmerjake pushed to add-structure at programmerjake/grant-tracking 2025-08-26 07:19:26 +00:00
fc04ac0f76 add rest of issues
f9bff4c415 final script fixes
cc7aa3c7b1 dump expected issue contents even when issue doesn't yet exist
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programmerjake opened issue libre-chip/grant-tracking#22 2025-08-26 07:15:34 +00:00
NLnet 2024-12-324 Attempt Proof that our CPU but with zeroed outputs for all eventually-cancelled instructions is equivalent to our real CPU design
programmerjake opened issue libre-chip/grant-tracking#21 2025-08-26 07:14:28 +00:00
NLnet 2024-12-324 Write Rocq and HDL logic for tracking which instructions will eventually be cancelled and which will eventually be retired.
programmerjake opened issue libre-chip/grant-tracking#20 2025-08-26 07:13:12 +00:00
NLnet 2024-12-324 adding order-violation detection logic
programmerjake opened issue libre-chip/grant-tracking#19 2025-08-26 07:12:03 +00:00
NLnet 2024-12-324 adding atomics: lr/sc, atomic fetch-add (or other fetch-op)