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2 commits
393f78a14d ... 8d030ac65d

Author SHA1 Message Date
Jacob Lifshay
8d030ac65d
sim/interpreter: add addresses to instruction listing
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2024-12-12 16:25:38 -08:00
Jacob Lifshay
562c479b62
sim/interpreter: fix StatePartLayout name in debug output 2024-12-12 15:06:17 -08:00
8 changed files with 299 additions and 298 deletions
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3
crates/fayalite/src/sim/interpreter.rs
View file

@ -565,6 +565,7 @@ impl<BK: InsnsBuildingKind> fmt::Debug for InsnDebug<'_, BK> {
if let Some(source_location) = self.source_location {
writeln!(f, "// at: {source_location}")?;
}
write!(f, "{}: ", self.address)?;
self.insn.debug_fmt(f, self.labels, Some(self.state_layout))
}
}
@ -1711,7 +1712,7 @@ impl<K: StatePartKind, BK: InsnsBuildingKind> fmt::Debug for StatePartLayout<K,
layout_data,
_phantom: _,
} = self;
write!(f, "StatePartAllocationLayout<{}>", K::NAME)?;
write!(f, "StatePartLayout<{}>", K::NAME)?;
let mut debug_struct = f.debug_struct("");
debug_struct
.field("len", &debug_data.len())

16
crates/fayalite/tests/sim/expected/connect_const.txt
View file

@ -3,12 +3,12 @@ Simulation {
insns: Insns {
state_layout: StateLayout {
ty: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 2,
debug_data: [
SlotDebugData {
@ -23,7 +23,7 @@ Simulation {
..
},
},
memories: StatePartAllocationLayout<Memories> {
memories: StatePartLayout<Memories> {
len: 0,
debug_data: [],
layout_data: [],
@ -32,17 +32,17 @@ Simulation {
},
insns: [
// at: module-XXXXXXXXXX.rs:1:1
Const {
0: Const {
dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
value: 5,
},
// at: module-XXXXXXXXXX.rs:3:1
Copy {
1: Copy {
dest: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const: connect_const).connect_const::o", ty: UInt<8> },
src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
},
// at: module-XXXXXXXXXX.rs:1:1
Return,
2: Return,
],
..
},
@ -80,12 +80,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: UInt<8>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {

26
crates/fayalite/tests/sim/expected/connect_const_reset.txt
View file

@ -3,12 +3,12 @@ Simulation {
insns: Insns {
state_layout: StateLayout {
ty: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 5,
debug_data: [
SlotDebugData {
@ -35,7 +35,7 @@ Simulation {
..
},
},
memories: StatePartAllocationLayout<Memories> {
memories: StatePartLayout<Memories> {
len: 0,
debug_data: [],
layout_data: [],
@ -44,31 +44,31 @@ Simulation {
},
insns: [
// at: module-XXXXXXXXXX.rs:1:1
Const {
0: Const {
dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "", ty: Bool },
value: 1,
},
Copy {
1: Copy {
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "", ty: AsyncReset },
src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:4:1
Copy {
2: Copy {
dest: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "", ty: AsyncReset },
},
// at: module-XXXXXXXXXX.rs:1:1
Copy {
3: Copy {
dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
},
// at: module-XXXXXXXXXX.rs:5:1
Copy {
4: Copy {
dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", ty: Bool },
src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:1:1
Return,
5: Return,
],
..
},
@ -109,12 +109,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: Bool,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -143,12 +143,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: AsyncReset,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {

68
crates/fayalite/tests/sim/expected/counter_async.txt
View file

@ -3,7 +3,7 @@ Simulation {
insns: Insns {
state_layout: StateLayout {
ty: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 4,
debug_data: [
SlotDebugData {
@ -25,7 +25,7 @@ Simulation {
],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 10,
debug_data: [
SlotDebugData {
@ -72,7 +72,7 @@ Simulation {
..
},
},
memories: StatePartAllocationLayout<Memories> {
memories: StatePartLayout<Memories> {
len: 0,
debug_data: [],
layout_data: [],
@ -81,89 +81,89 @@ Simulation {
},
insns: [
// at: module-XXXXXXXXXX.rs:1:1
Const {
0: Const {
dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<1> },
value: 1,
},
Copy {
1: Copy {
dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
},
// at: module-XXXXXXXXXX.rs:3:1
IsNonZeroDestIsSmall {
2: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
},
// at: module-XXXXXXXXXX.rs:1:1
Const {
3: Const {
dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
value: 3,
},
// at: module-XXXXXXXXXX.rs:3:1
BranchIfZero {
4: BranchIfZero {
target: 6,
value: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
},
Copy {
5: Copy {
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:1:1
Add {
6: Add {
dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<5> },
lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
rhs: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<1> },
},
CastToUInt {
7: CastToUInt {
dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<5> },
dest_width: 4,
},
// at: module-XXXXXXXXXX.rs:4:1
Copy {
8: Copy {
dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:6:1
Copy {
9: Copy {
dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:3:1
IsNonZeroDestIsSmall {
10: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
},
AndSmall {
11: AndSmall {
dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
},
BranchIfSmallNonZero {
12: BranchIfSmallNonZero {
target: 16,
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
},
BranchIfSmallZero {
13: BranchIfSmallZero {
target: 17,
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
},
Copy {
14: Copy {
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
},
Branch {
15: Branch {
target: 17,
},
Copy {
16: Copy {
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
},
NotSmall {
17: NotSmall {
dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:1:1
Return,
18: Return,
],
..
},
@ -219,12 +219,12 @@ Simulation {
rst: AsyncReset,
},
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 2,
debug_data: [
SlotDebugData {
@ -249,12 +249,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -276,12 +276,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: AsyncReset,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -314,12 +314,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -348,12 +348,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: AsyncReset,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -382,12 +382,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {

62
crates/fayalite/tests/sim/expected/counter_sync.txt
View file

@ -3,7 +3,7 @@ Simulation {
insns: Insns {
state_layout: StateLayout {
ty: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 4,
debug_data: [
SlotDebugData {
@ -25,7 +25,7 @@ Simulation {
],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 9,
debug_data: [
SlotDebugData {
@ -68,7 +68,7 @@ Simulation {
..
},
},
memories: StatePartAllocationLayout<Memories> {
memories: StatePartLayout<Memories> {
len: 0,
debug_data: [],
layout_data: [],
@ -77,75 +77,75 @@ Simulation {
},
insns: [
// at: module-XXXXXXXXXX.rs:6:1
Copy {
0: Copy {
dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:1:1
Const {
1: Const {
dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: UInt<1> },
value: 1,
},
Add {
2: Add {
dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<5> },
lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
rhs: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: UInt<1> },
},
CastToUInt {
3: CastToUInt {
dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<5> },
dest_width: 4,
},
// at: module-XXXXXXXXXX.rs:4:1
Copy {
4: Copy {
dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:3:1
IsNonZeroDestIsSmall {
5: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset },
},
// at: module-XXXXXXXXXX.rs:1:1
Const {
6: Const {
dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
value: 3,
},
// at: module-XXXXXXXXXX.rs:3:1
IsNonZeroDestIsSmall {
7: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
},
AndSmall {
8: AndSmall {
dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
},
BranchIfSmallZero {
9: BranchIfSmallZero {
target: 14,
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
},
BranchIfSmallNonZero {
10: BranchIfSmallNonZero {
target: 13,
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
},
Copy {
11: Copy {
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
},
Branch {
12: Branch {
target: 14,
},
Copy {
13: Copy {
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
},
NotSmall {
14: NotSmall {
dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:1:1
Return,
15: Return,
],
..
},
@ -200,12 +200,12 @@ Simulation {
rst: SyncReset,
},
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 2,
debug_data: [
SlotDebugData {
@ -230,12 +230,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -257,12 +257,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: SyncReset,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -295,12 +295,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -329,12 +329,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: SyncReset,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -363,12 +363,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {

248
crates/fayalite/tests/sim/expected/enums.txt
View file

@ -3,7 +3,7 @@ Simulation {
insns: Insns {
state_layout: StateLayout {
ty: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 5,
debug_data: [
SlotDebugData {
@ -33,7 +33,7 @@ Simulation {
],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 82,
debug_data: [
SlotDebugData {
@ -388,7 +388,7 @@ Simulation {
..
},
},
memories: StatePartAllocationLayout<Memories> {
memories: StatePartLayout<Memories> {
len: 0,
debug_data: [],
layout_data: [],
@ -397,480 +397,480 @@ Simulation {
},
insns: [
// at: module-XXXXXXXXXX.rs:1:1
Const {
0: Const {
dest: StatePartIndex<BigSlots>(72), // SlotDebugData { name: "", ty: UInt<4> },
value: 0,
},
SliceInt {
1: SliceInt {
dest: StatePartIndex<BigSlots>(61), // SlotDebugData { name: "", ty: UInt<2> },
src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
start: 2,
len: 2,
},
CastToSInt {
2: CastToSInt {
dest: StatePartIndex<BigSlots>(62), // SlotDebugData { name: "", ty: SInt<2> },
src: StatePartIndex<BigSlots>(61), // SlotDebugData { name: "", ty: UInt<2> },
dest_width: 2,
},
Const {
3: Const {
dest: StatePartIndex<BigSlots>(54), // SlotDebugData { name: "", ty: UInt<2> },
value: 2,
},
SliceInt {
4: SliceInt {
dest: StatePartIndex<BigSlots>(41), // SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
start: 1,
len: 1,
},
Copy {
5: Copy {
dest: StatePartIndex<BigSlots>(42), // SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(41), // SlotDebugData { name: "", ty: UInt<1> },
},
Copy {
6: Copy {
dest: StatePartIndex<BigSlots>(60), // SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(42), // SlotDebugData { name: "", ty: Bool },
},
SliceInt {
7: SliceInt {
dest: StatePartIndex<BigSlots>(38), // SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
start: 0,
len: 1,
},
Copy {
8: Copy {
dest: StatePartIndex<BigSlots>(39), // SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(38), // SlotDebugData { name: "", ty: UInt<1> },
},
Copy {
9: Copy {
dest: StatePartIndex<BigSlots>(40), // SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(39), // SlotDebugData { name: "", ty: Bool },
},
Copy {
10: Copy {
dest: StatePartIndex<BigSlots>(36), // SlotDebugData { name: ".0", ty: UInt<1> },
src: StatePartIndex<BigSlots>(40), // SlotDebugData { name: "", ty: UInt<1> },
},
Copy {
11: Copy {
dest: StatePartIndex<BigSlots>(37), // SlotDebugData { name: ".1", ty: Bool },
src: StatePartIndex<BigSlots>(42), // SlotDebugData { name: "", ty: Bool },
},
Copy {
12: Copy {
dest: StatePartIndex<BigSlots>(58), // SlotDebugData { name: "[0]", ty: UInt<1> },
src: StatePartIndex<BigSlots>(40), // SlotDebugData { name: "", ty: UInt<1> },
},
Copy {
13: Copy {
dest: StatePartIndex<BigSlots>(59), // SlotDebugData { name: "[1]", ty: UInt<1> },
src: StatePartIndex<BigSlots>(60), // SlotDebugData { name: "", ty: UInt<1> },
},
Copy {
14: Copy {
dest: StatePartIndex<BigSlots>(55), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
src: StatePartIndex<BigSlots>(58), // SlotDebugData { name: "[0]", ty: UInt<1> },
},
Copy {
15: Copy {
dest: StatePartIndex<BigSlots>(56), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
src: StatePartIndex<BigSlots>(59), // SlotDebugData { name: "[1]", ty: UInt<1> },
},
Copy {
16: Copy {
dest: StatePartIndex<BigSlots>(57), // SlotDebugData { name: ".b", ty: SInt<2> },
src: StatePartIndex<BigSlots>(62), // SlotDebugData { name: "", ty: SInt<2> },
},
Copy {
17: Copy {
dest: StatePartIndex<BigSlots>(50), // SlotDebugData { name: ".0", ty: UInt<2> },
src: StatePartIndex<BigSlots>(54), // SlotDebugData { name: "", ty: UInt<2> },
},
Copy {
18: Copy {
dest: StatePartIndex<BigSlots>(51), // SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
src: StatePartIndex<BigSlots>(55), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
},
Copy {
19: Copy {
dest: StatePartIndex<BigSlots>(52), // SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
src: StatePartIndex<BigSlots>(56), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
},
Copy {
20: Copy {
dest: StatePartIndex<BigSlots>(53), // SlotDebugData { name: ".1.b", ty: SInt<2> },
src: StatePartIndex<BigSlots>(57), // SlotDebugData { name: ".b", ty: SInt<2> },
},
Shl {
21: Shl {
dest: StatePartIndex<BigSlots>(63), // SlotDebugData { name: "", ty: UInt<2> },
lhs: StatePartIndex<BigSlots>(52), // SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
rhs: 1,
},
Or {
22: Or {
dest: StatePartIndex<BigSlots>(64), // SlotDebugData { name: "", ty: UInt<2> },
lhs: StatePartIndex<BigSlots>(51), // SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
rhs: StatePartIndex<BigSlots>(63), // SlotDebugData { name: "", ty: UInt<2> },
},
CastToUInt {
23: CastToUInt {
dest: StatePartIndex<BigSlots>(65), // SlotDebugData { name: "", ty: UInt<2> },
src: StatePartIndex<BigSlots>(53), // SlotDebugData { name: ".1.b", ty: SInt<2> },
dest_width: 2,
},
Shl {
24: Shl {
dest: StatePartIndex<BigSlots>(66), // SlotDebugData { name: "", ty: UInt<4> },
lhs: StatePartIndex<BigSlots>(65), // SlotDebugData { name: "", ty: UInt<2> },
rhs: 2,
},
Or {
25: Or {
dest: StatePartIndex<BigSlots>(67), // SlotDebugData { name: "", ty: UInt<4> },
lhs: StatePartIndex<BigSlots>(64), // SlotDebugData { name: "", ty: UInt<2> },
rhs: StatePartIndex<BigSlots>(66), // SlotDebugData { name: "", ty: UInt<4> },
},
Shl {
26: Shl {
dest: StatePartIndex<BigSlots>(68), // SlotDebugData { name: "", ty: UInt<6> },
lhs: StatePartIndex<BigSlots>(67), // SlotDebugData { name: "", ty: UInt<4> },
rhs: 2,
},
Or {
27: Or {
dest: StatePartIndex<BigSlots>(69), // SlotDebugData { name: "", ty: UInt<6> },
lhs: StatePartIndex<BigSlots>(50), // SlotDebugData { name: ".0", ty: UInt<2> },
rhs: StatePartIndex<BigSlots>(68), // SlotDebugData { name: "", ty: UInt<6> },
},
CastToUInt {
28: CastToUInt {
dest: StatePartIndex<BigSlots>(70), // SlotDebugData { name: "", ty: UInt<6> },
src: StatePartIndex<BigSlots>(69), // SlotDebugData { name: "", ty: UInt<6> },
dest_width: 6,
},
Copy {
29: Copy {
dest: StatePartIndex<BigSlots>(71), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
src: StatePartIndex<BigSlots>(70), // SlotDebugData { name: "", ty: UInt<6> },
},
Const {
30: Const {
dest: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
value: 1,
},
CmpEq {
31: CmpEq {
dest: StatePartIndex<BigSlots>(32), // SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
rhs: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
},
Copy {
32: Copy {
dest: StatePartIndex<BigSlots>(33), // SlotDebugData { name: ".0", ty: UInt<2> },
src: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
},
Copy {
33: Copy {
dest: StatePartIndex<BigSlots>(34), // SlotDebugData { name: ".1.0", ty: UInt<1> },
src: StatePartIndex<BigSlots>(36), // SlotDebugData { name: ".0", ty: UInt<1> },
},
Copy {
34: Copy {
dest: StatePartIndex<BigSlots>(35), // SlotDebugData { name: ".1.1", ty: Bool },
src: StatePartIndex<BigSlots>(37), // SlotDebugData { name: ".1", ty: Bool },
},
Copy {
35: Copy {
dest: StatePartIndex<BigSlots>(43), // SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(35), // SlotDebugData { name: ".1.1", ty: Bool },
},
Shl {
36: Shl {
dest: StatePartIndex<BigSlots>(44), // SlotDebugData { name: "", ty: UInt<2> },
lhs: StatePartIndex<BigSlots>(43), // SlotDebugData { name: "", ty: UInt<1> },
rhs: 1,
},
Or {
37: Or {
dest: StatePartIndex<BigSlots>(45), // SlotDebugData { name: "", ty: UInt<2> },
lhs: StatePartIndex<BigSlots>(34), // SlotDebugData { name: ".1.0", ty: UInt<1> },
rhs: StatePartIndex<BigSlots>(44), // SlotDebugData { name: "", ty: UInt<2> },
},
Shl {
38: Shl {
dest: StatePartIndex<BigSlots>(46), // SlotDebugData { name: "", ty: UInt<4> },
lhs: StatePartIndex<BigSlots>(45), // SlotDebugData { name: "", ty: UInt<2> },
rhs: 2,
},
Or {
39: Or {
dest: StatePartIndex<BigSlots>(47), // SlotDebugData { name: "", ty: UInt<4> },
lhs: StatePartIndex<BigSlots>(33), // SlotDebugData { name: ".0", ty: UInt<2> },
rhs: StatePartIndex<BigSlots>(46), // SlotDebugData { name: "", ty: UInt<4> },
},
CastToUInt {
40: CastToUInt {
dest: StatePartIndex<BigSlots>(48), // SlotDebugData { name: "", ty: UInt<6> },
src: StatePartIndex<BigSlots>(47), // SlotDebugData { name: "", ty: UInt<4> },
dest_width: 6,
},
Copy {
41: Copy {
dest: StatePartIndex<BigSlots>(49), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
src: StatePartIndex<BigSlots>(48), // SlotDebugData { name: "", ty: UInt<6> },
},
Const {
42: Const {
dest: StatePartIndex<BigSlots>(29), // SlotDebugData { name: "", ty: UInt<2> },
value: 0,
},
CmpEq {
43: CmpEq {
dest: StatePartIndex<BigSlots>(30), // SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
rhs: StatePartIndex<BigSlots>(29), // SlotDebugData { name: "", ty: UInt<2> },
},
Copy {
44: Copy {
dest: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<6> },
src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
},
SliceInt {
45: SliceInt {
dest: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<2> },
src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<6> },
start: 2,
len: 2,
},
SliceInt {
46: SliceInt {
dest: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<2> },
start: 0,
len: 1,
},
SliceInt {
47: SliceInt {
dest: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<2> },
start: 1,
len: 1,
},
Copy {
48: Copy {
dest: StatePartIndex<BigSlots>(17), // SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<1> },
},
Copy {
49: Copy {
dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: ".0", ty: UInt<1> },
src: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: UInt<1> },
},
Copy {
50: Copy {
dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: ".1", ty: Bool },
src: StatePartIndex<BigSlots>(17), // SlotDebugData { name: "", ty: Bool },
},
Copy {
51: Copy {
dest: StatePartIndex<BigSlots>(73), // SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: ".1", ty: Bool },
},
Shl {
52: Shl {
dest: StatePartIndex<BigSlots>(74), // SlotDebugData { name: "", ty: UInt<2> },
lhs: StatePartIndex<BigSlots>(73), // SlotDebugData { name: "", ty: UInt<1> },
rhs: 1,
},
Or {
53: Or {
dest: StatePartIndex<BigSlots>(75), // SlotDebugData { name: "", ty: UInt<2> },
lhs: StatePartIndex<BigSlots>(11), // SlotDebugData { name: ".0", ty: UInt<1> },
rhs: StatePartIndex<BigSlots>(74), // SlotDebugData { name: "", ty: UInt<2> },
},
CastToUInt {
54: CastToUInt {
dest: StatePartIndex<BigSlots>(76), // SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(75), // SlotDebugData { name: "", ty: UInt<2> },
dest_width: 4,
},
SliceInt {
55: SliceInt {
dest: StatePartIndex<BigSlots>(23), // SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<6> },
start: 2,
len: 4,
},
SliceInt {
56: SliceInt {
dest: StatePartIndex<BigSlots>(24), // SlotDebugData { name: "", ty: UInt<2> },
src: StatePartIndex<BigSlots>(23), // SlotDebugData { name: "", ty: UInt<4> },
start: 0,
len: 2,
},
SliceInt {
57: SliceInt {
dest: StatePartIndex<BigSlots>(25), // SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(24), // SlotDebugData { name: "", ty: UInt<2> },
start: 0,
len: 1,
},
SliceInt {
58: SliceInt {
dest: StatePartIndex<BigSlots>(26), // SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(24), // SlotDebugData { name: "", ty: UInt<2> },
start: 1,
len: 1,
},
Copy {
59: Copy {
dest: StatePartIndex<BigSlots>(21), // SlotDebugData { name: "[0]", ty: UInt<1> },
src: StatePartIndex<BigSlots>(25), // SlotDebugData { name: "", ty: UInt<1> },
},
Copy {
60: Copy {
dest: StatePartIndex<BigSlots>(22), // SlotDebugData { name: "[1]", ty: UInt<1> },
src: StatePartIndex<BigSlots>(26), // SlotDebugData { name: "", ty: UInt<1> },
},
SliceInt {
61: SliceInt {
dest: StatePartIndex<BigSlots>(27), // SlotDebugData { name: "", ty: UInt<2> },
src: StatePartIndex<BigSlots>(23), // SlotDebugData { name: "", ty: UInt<4> },
start: 2,
len: 2,
},
CastToSInt {
62: CastToSInt {
dest: StatePartIndex<BigSlots>(28), // SlotDebugData { name: "", ty: SInt<2> },
src: StatePartIndex<BigSlots>(27), // SlotDebugData { name: "", ty: UInt<2> },
dest_width: 2,
},
Copy {
63: Copy {
dest: StatePartIndex<BigSlots>(18), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
src: StatePartIndex<BigSlots>(21), // SlotDebugData { name: "[0]", ty: UInt<1> },
},
Copy {
64: Copy {
dest: StatePartIndex<BigSlots>(19), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
src: StatePartIndex<BigSlots>(22), // SlotDebugData { name: "[1]", ty: UInt<1> },
},
Copy {
65: Copy {
dest: StatePartIndex<BigSlots>(20), // SlotDebugData { name: ".b", ty: SInt<2> },
src: StatePartIndex<BigSlots>(28), // SlotDebugData { name: "", ty: SInt<2> },
},
Shl {
66: Shl {
dest: StatePartIndex<BigSlots>(77), // SlotDebugData { name: "", ty: UInt<2> },
lhs: StatePartIndex<BigSlots>(19), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
rhs: 1,
},
Or {
67: Or {
dest: StatePartIndex<BigSlots>(78), // SlotDebugData { name: "", ty: UInt<2> },
lhs: StatePartIndex<BigSlots>(18), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
rhs: StatePartIndex<BigSlots>(77), // SlotDebugData { name: "", ty: UInt<2> },
},
CastToUInt {
68: CastToUInt {
dest: StatePartIndex<BigSlots>(79), // SlotDebugData { name: "", ty: UInt<2> },
src: StatePartIndex<BigSlots>(20), // SlotDebugData { name: ".b", ty: SInt<2> },
dest_width: 2,
},
Shl {
69: Shl {
dest: StatePartIndex<BigSlots>(80), // SlotDebugData { name: "", ty: UInt<4> },
lhs: StatePartIndex<BigSlots>(79), // SlotDebugData { name: "", ty: UInt<2> },
rhs: 2,
},
Or {
70: Or {
dest: StatePartIndex<BigSlots>(81), // SlotDebugData { name: "", ty: UInt<4> },
lhs: StatePartIndex<BigSlots>(78), // SlotDebugData { name: "", ty: UInt<2> },
rhs: StatePartIndex<BigSlots>(80), // SlotDebugData { name: "", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:8:1
AndBigWithSmallImmediate {
71: AndBigWithSmallImmediate {
dest: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
lhs: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
rhs: 3,
},
// at: module-XXXXXXXXXX.rs:15:1
BranchIfSmallNeImmediate {
72: BranchIfSmallNeImmediate {
target: 75,
lhs: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
rhs: 0,
},
// at: module-XXXXXXXXXX.rs:16:1
Copy {
73: Copy {
dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
src: StatePartIndex<BigSlots>(29), // SlotDebugData { name: "", ty: UInt<2> },
},
// at: module-XXXXXXXXXX.rs:17:1
Copy {
74: Copy {
dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
src: StatePartIndex<BigSlots>(72), // SlotDebugData { name: "", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:15:1
BranchIfSmallNeImmediate {
75: BranchIfSmallNeImmediate {
target: 78,
lhs: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
rhs: 1,
},
// at: module-XXXXXXXXXX.rs:18:1
Copy {
76: Copy {
dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
src: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
},
// at: module-XXXXXXXXXX.rs:19:1
Copy {
77: Copy {
dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
src: StatePartIndex<BigSlots>(76), // SlotDebugData { name: "", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:15:1
BranchIfSmallNeImmediate {
78: BranchIfSmallNeImmediate {
target: 81,
lhs: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
rhs: 2,
},
// at: module-XXXXXXXXXX.rs:20:1
Copy {
79: Copy {
dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
src: StatePartIndex<BigSlots>(54), // SlotDebugData { name: "", ty: UInt<2> },
},
// at: module-XXXXXXXXXX.rs:21:1
Copy {
80: Copy {
dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
src: StatePartIndex<BigSlots>(81), // SlotDebugData { name: "", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:8:1
IsNonZeroDestIsSmall {
81: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.rst", ty: SyncReset },
},
// at: module-XXXXXXXXXX.rs:1:1
Const {
82: Const {
dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<6> },
value: 0,
},
Copy {
83: Copy {
dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<6> },
},
// at: module-XXXXXXXXXX.rs:9:1
BranchIfZero {
84: BranchIfZero {
target: 92,
value: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:10:1
BranchIfZero {
85: BranchIfZero {
target: 87,
value: StatePartIndex<BigSlots>(30), // SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:11:1
Copy {
86: Copy {
dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
},
// at: module-XXXXXXXXXX.rs:10:1
BranchIfNonZero {
87: BranchIfNonZero {
target: 92,
value: StatePartIndex<BigSlots>(30), // SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:12:1
BranchIfZero {
88: BranchIfZero {
target: 90,
value: StatePartIndex<BigSlots>(32), // SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:13:1
Copy {
89: Copy {
dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
src: StatePartIndex<BigSlots>(49), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
},
// at: module-XXXXXXXXXX.rs:12:1
BranchIfNonZero {
90: BranchIfNonZero {
target: 92,
value: StatePartIndex<BigSlots>(32), // SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:14:1
Copy {
91: Copy {
dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
src: StatePartIndex<BigSlots>(71), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
},
// at: module-XXXXXXXXXX.rs:8:1
IsNonZeroDestIsSmall {
92: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.clk", ty: Clock },
},
AndSmall {
93: AndSmall {
dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
},
BranchIfSmallZero {
94: BranchIfSmallZero {
target: 99,
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
},
BranchIfSmallNonZero {
95: BranchIfSmallNonZero {
target: 98,
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
},
Copy {
96: Copy {
dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
},
Branch {
97: Branch {
target: 99,
},
Copy {
98: Copy {
dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
},
NotSmall {
99: NotSmall {
dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:1:1
Return,
100: Return,
],
..
},
@ -999,12 +999,12 @@ Simulation {
rst: SyncReset,
},
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 2,
debug_data: [
SlotDebugData {
@ -1029,12 +1029,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -1056,12 +1056,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: SyncReset,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -1094,12 +1094,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -1128,12 +1128,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: SyncReset,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -1162,12 +1162,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -1196,12 +1196,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -1230,12 +1230,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: Bool,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -1264,12 +1264,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: UInt<2>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -1298,12 +1298,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: UInt<2>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {

78
crates/fayalite/tests/sim/expected/mod1.txt
View file

@ -3,12 +3,12 @@ Simulation {
insns: Insns {
state_layout: StateLayout {
ty: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 17,
debug_data: [
SlotDebugData {
@ -83,7 +83,7 @@ Simulation {
..
},
},
memories: StatePartAllocationLayout<Memories> {
memories: StatePartLayout<Memories> {
len: 0,
debug_data: [],
layout_data: [],
@ -92,90 +92,90 @@ Simulation {
},
insns: [
// at: module-XXXXXXXXXX.rs:4:1
Copy {
0: Copy {
dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i2", ty: SInt<2> },
},
Copy {
1: Copy {
dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:2:1
Copy {
2: Copy {
dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
},
Copy {
3: Copy {
dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
},
// at: module-XXXXXXXXXX-2.rs:1:1
Const {
4: Const {
dest: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<4> },
value: 15,
},
Const {
5: Const {
dest: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<4> },
value: 5,
},
CmpLt {
6: CmpLt {
dest: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<4> },
rhs: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
},
CastToUInt {
7: CastToUInt {
dest: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
dest_width: 4,
},
// at: module-XXXXXXXXXX-2.rs:7:1
Copy {
8: Copy {
dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<4> },
},
// at: module-XXXXXXXXXX-2.rs:8:1
BranchIfZero {
9: BranchIfZero {
target: 11,
value: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX-2.rs:9:1
Copy {
10: Copy {
dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
src: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:2:1
Copy {
11: Copy {
dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
src: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:4:1
Copy {
12: Copy {
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o2", ty: UInt<4> },
src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
},
// at: module-XXXXXXXXXX-2.rs:1:1
CastToSInt {
13: CastToSInt {
dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "", ty: SInt<2> },
src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
dest_width: 2,
},
// at: module-XXXXXXXXXX-2.rs:6:1
Copy {
14: Copy {
dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "", ty: SInt<2> },
},
// at: module-XXXXXXXXXX.rs:2:1
Copy {
15: Copy {
dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
},
// at: module-XXXXXXXXXX.rs:4:1
Copy {
16: Copy {
dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o", ty: SInt<2> },
src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
},
// at: module-XXXXXXXXXX.rs:1:1
Return,
17: Return,
],
..
},
@ -237,12 +237,12 @@ Simulation {
o2: UInt<4>,
},
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 4,
debug_data: [
SlotDebugData {
@ -275,12 +275,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -302,12 +302,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: SInt<2>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -329,12 +329,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: SInt<2>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -356,12 +356,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -394,12 +394,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -428,12 +428,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: SInt<2>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -462,12 +462,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: SInt<2>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -496,12 +496,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {

96
crates/fayalite/tests/sim/expected/shift_register.txt
View file

@ -3,7 +3,7 @@ Simulation {
insns: Insns {
state_layout: StateLayout {
ty: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 4,
debug_data: [
SlotDebugData {
@ -25,7 +25,7 @@ Simulation {
],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 13,
debug_data: [
SlotDebugData {
@ -84,7 +84,7 @@ Simulation {
..
},
},
memories: StatePartAllocationLayout<Memories> {
memories: StatePartLayout<Memories> {
len: 0,
debug_data: [],
layout_data: [],
@ -93,136 +93,136 @@ Simulation {
},
insns: [
// at: module-XXXXXXXXXX.rs:13:1
Copy {
0: Copy {
dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool },
src: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:12:1
Copy {
1: Copy {
dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:10:1
Copy {
2: Copy {
dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:8:1
Copy {
3: Copy {
dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:6:1
Copy {
4: Copy {
dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:5:1
IsNonZeroDestIsSmall {
5: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset },
},
// at: module-XXXXXXXXXX.rs:1:1
Const {
6: Const {
dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
value: 0,
},
// at: module-XXXXXXXXXX.rs:5:1
IsNonZeroDestIsSmall {
7: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock },
},
AndSmall {
8: AndSmall {
dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
},
BranchIfSmallZero {
9: BranchIfSmallZero {
target: 14,
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
},
BranchIfSmallNonZero {
10: BranchIfSmallNonZero {
target: 13,
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
},
Copy {
11: Copy {
dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
},
Branch {
12: Branch {
target: 14,
},
Copy {
13: Copy {
dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:7:1
BranchIfSmallZero {
14: BranchIfSmallZero {
target: 19,
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
},
BranchIfSmallNonZero {
15: BranchIfSmallNonZero {
target: 18,
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
},
Copy {
16: Copy {
dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
},
Branch {
17: Branch {
target: 19,
},
Copy {
18: Copy {
dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:9:1
BranchIfSmallZero {
19: BranchIfSmallZero {
target: 24,
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
},
BranchIfSmallNonZero {
20: BranchIfSmallNonZero {
target: 23,
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
},
Copy {
21: Copy {
dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
},
Branch {
22: Branch {
target: 24,
},
Copy {
23: Copy {
dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:11:1
BranchIfSmallZero {
24: BranchIfSmallZero {
target: 29,
value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
},
BranchIfSmallNonZero {
25: BranchIfSmallNonZero {
target: 28,
value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
},
Copy {
26: Copy {
dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
},
Branch {
27: Branch {
target: 29,
},
Copy {
28: Copy {
dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:5:1
NotSmall {
29: NotSmall {
dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:1:1
Return,
30: Return,
],
..
},
@ -281,12 +281,12 @@ Simulation {
rst: SyncReset,
},
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 2,
debug_data: [
SlotDebugData {
@ -311,12 +311,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -338,12 +338,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: SyncReset,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -376,12 +376,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -410,12 +410,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: SyncReset,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -444,12 +444,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: Bool,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -478,12 +478,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: Bool,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {