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yosys/tests/various
Emil J 468ba27d91
Merge pull request #6078 from YosysHQ/emil/hierarchy-fix-keep-cache
hierarchy: fix keep cache usage by caching false too
2026-08-03 15:54:50 +00:00
..
dynamic_part_select Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
.gitignore Ignore some generated files 2026-04-16 11:00:44 +02:00
abc9.v Move rename logic to abc_ops_reintegrate 2026-06-19 10:46:47 +01:00
abc9.ys Move rename logic to abc_ops_reintegrate 2026-06-19 10:46:47 +01:00
abstract_init.ys
abstract_initstates.ys
abstract_state.ys
abstract_value.ys
aiger2.ys
aiger_dff.ys
async.sh Make out of tree build testing possible 2026-05-19 14:26:07 +02:00
async.v
attrib05_port_conn.v End of file fix 2026-06-23 07:23:41 +02:00
attrib05_port_conn.ys
attrib07_func_call.v End of file fix 2026-06-23 07:23:41 +02:00
attrib07_func_call.ys
autoname.ys autoname: selection determines what gets renamed, not the name it gets renamed to 2026-07-17 22:48:46 +02:00
blackbox_wb.ys
box_derive.ys box_derive: rename -apply to -apply_derived_type 2025-10-13 17:24:32 +02:00
bufnorm_opt_clean.ys bufnorm: Refactor and fix incremental bufNormalize 2025-09-29 08:21:28 +02:00
bug1496.ys
bug1531.ys Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
bug1614.ys
bug1710.ys
bug1745.ys Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
bug1781.ys
bug1876.ys
bug2014.ys
bug3462.ys
bug3515.v tests: Add bug3515 2025-11-25 07:04:34 +13:00
bug3515.ys End of file fix 2026-06-23 07:23:41 +02:00
bug3879.ys
bug4082.ys
bug4865.ys Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
bug4909.ys End of file fix 2026-06-23 07:23:41 +02:00
cellarray_array_connections.ys
celledges_shift.ys
check.ys
check_2.ys
check_3.ys
check_4.ys Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
check_nolatches.ys Fix (async latch). 2026-06-24 13:01:52 +02:00
chformal_check.ys
chformal_coverenable.ys
chparam.sh Make out of tree build testing possible 2026-05-19 14:26:07 +02:00
clk2fflogic_effects.sh Make out of tree build testing possible 2026-05-19 14:26:07 +02:00
clk2fflogic_effects.sv
const_arg_loop.sv
const_arg_loop.ys
const_cmdline.ys Attr file:line. 2026-07-31 10:31:44 +02:00
const_cmdline_nested.sh Add nesting test. 2026-07-31 10:31:44 +02:00
const_func.sv
const_func.ys
const_func_block_var.v
const_func_block_var.ys
const_shift_empty_arg.ys Fix segfault from shift with 0-width signed arg. 2026-02-12 22:03:42 -06:00
constant_drive_conflict.ys
constcomment.ys
constmsk_test.v
constmsk_test.ys
constmsk_testmap.v
countbits.sv
countbits.ys
cutpoint_blackbox.ys
cutpoint_whole.ys
debugon.ys Add -on/-off modes to debug pass 2026-01-15 12:07:26 -08:00
deminout_unused.ys End of file fix 2026-06-23 07:23:41 +02:00
design.ys
design1.ys
design2.ys
design_equal_fail.ys Implement design_equal command 2025-12-21 21:47:40 +00:00
design_equal_pass.ys Implement design_equal command 2025-12-21 21:47:40 +00:00
dynamic_part_select.ys Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
elab_sys_tasks.sv
elab_sys_tasks.ys
equiv_assume.ys
equiv_make_make_assert.ys
equiv_opt_multiclock.ys
equiv_opt_undef.ys Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
exec.ys
ezcmdline_dummy_solver Remove FHS dependency by replacing /bin/sh with /usr/bin/env sh 2026-04-23 15:55:11 +02:00
ezcmdline_plugin.cc Add test for ezCmdlineSAT 2026-01-20 09:28:00 -08:00
ezcmdline_plugin.sh Update CI scripts for CMake 2026-06-03 08:58:11 +00:00
fib.v
fib.ys
fib_tern.v
fib_tern.ys
formalff_declockgate.ys
fsm-arst.ys Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
func_port_implied_dir.sv
func_port_implied_dir.ys
gen_if_null.v
gen_if_null.ys
generate_mk.py Convert gen-tests shell script to python 2026-04-16 11:00:44 +02:00
global_scope.ys
gzip_verilog.v.gz
gzip_verilog.ys
help.ys
hierarchy.sh Make out of tree build testing possible 2026-05-19 14:26:07 +02:00
hierarchy_defer.ys
hierarchy_generate.ys
hierarchy_param.ys
hierarchy_recursive.v hierarchy: regression test for keep cache 2026-08-03 17:36:49 +02:00
hierarchy_recursive.ys hierarchy: regression test for keep cache 2026-08-03 17:36:49 +02:00
ice40_mince_abc9.ys
integer_range_bad_syntax.ys
integer_real_bad_syntax.ys
json_escape_chars.ys
json_param_defaults.v Add tests 2026-02-11 08:10:57 -08:00
json_param_defaults.ys Don't dump params by default 2026-02-11 08:33:39 -08:00
json_scopeinfo.ys
keep_hierarchy.ys
lcov.gold
lcov.v
lcov.ys
logger_cmd_error.sh Make out of tree build testing possible 2026-05-19 14:26:07 +02:00
logger_error.ys
logger_fail.sh Make out of tree build testing possible 2026-05-19 14:26:07 +02:00
logger_nowarning.ys
logger_warn.ys
logger_warning.ys
logic_param_simple.ys
mem2reg.ys
memory_word_as_index.data
memory_word_as_index.v
memory_word_as_index.ys
muxcover.ys
muxcover_index.ys Use -assert-none. 2026-06-22 11:12:00 +02:00
muxpack.v Merge 'origin/main' into emil/muxpack-fix-chain. 2026-08-03 11:50:21 +02:00
muxpack.ys muxpack: reject slicing of predecessor Y ports in mux chain 2026-05-13 10:27:05 +02:00
muxpack_wide_y.ys Regression test for #5765 2026-03-30 08:59:28 -07:00
param_struct.ys
peepopt.ys peepopt: add shiftpow2 pattern 2026-05-31 02:01:32 +02:00
peepopt_formal.ys
plugin.cc
plugin.sh Update CI scripts for CMake 2026-06-03 08:58:11 +00:00
pmgen_reduce.ys
pmux2shiftx.v
pmux2shiftx.ys
port_sign_extend.v
port_sign_extend.ys
primitives.ys
printattr.ys
rand_const.sv
rand_const.ys
reg_wire_error.sv End of file fix 2026-06-23 07:23:41 +02:00
reg_wire_error.ys
rename_scramble_name.ys
rename_unescape.ys
rename_wire_move_to_cell.ys
rtlil_signed_attribute.ys
rtlil_z_bits.ys
scopeinfo.ys End of file fix 2026-06-23 07:23:41 +02:00
scratchpad.ys
script.ys
setundef.sv
setundef.ys
setundef_selection.ys changed rtlil to verilog. setundef_selection_ff stays rtlil because we use specific cell names if write in verilog yosys assign name that can change 2026-03-08 20:14:03 -04:00
setundef_selection_ff.il setundef: add tests for selection in -zero, -undriven, and -init modes. also made setundef.cc clearer 2026-03-06 18:12:03 -05:00
setundef_selection_undriven.v changed rtlil to verilog. setundef_selection_ff stays rtlil because we use specific cell names if write in verilog yosys assign name that can change 2026-03-08 20:14:03 -04:00
sformatf.ys
shregmap.v Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
shregmap.ys
signed.ys
signext.ys
sim_const.ys End of file fix 2026-06-23 07:23:41 +02:00
specify.v
specify.ys specify: fix test 2026-02-03 18:40:32 +01:00
splitnets.ys
src.ys
sta.ys
stat.ys Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
stat_area_by_width.lib Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
stat_hierarchy.ys Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
stat_high_level.ys End of file fix 2026-06-23 07:23:41 +02:00
stat_high_level2.ys End of file fix 2026-06-23 07:23:41 +02:00
struct_access.sv
struct_access.ys
sub.v
submod.ys
submod_extract.ys
sv_defines.ys
sv_defines_dup.ys
sv_defines_mismatch.ys
sv_defines_too_few.ys
sv_implicit_ports.sh Make out of tree build testing possible 2026-05-19 14:26:07 +02:00
svalways.sh proc: ignore nosync temporaries in always_latch checks 2026-05-26 00:56:07 +08:00
synth_latch_warning.ys Fixup level policy. 2026-06-18 18:00:51 +02:00
tcl_apis.tcl
tcl_apis.v
tcl_apis.ys
timeest.ys timeest: Add top ports launching/sampling 2025-11-03 14:21:28 +01:00
wrapcell.ys
wreduce.ys
wreduce2.ys
write_gzip.ys
xaiger.ys